+ [(set_attr "itanium_class" "ialu")
+ (set_attr "predicable" "no")])
+
+(define_insn "prologue_allocate_stack_pr"
+ [(cond_exec (match_operator 0 ("predicate_operator")
+ [(match_operand:BI 1 ("register_operand") ("c,c,c"))
+ (const_int 0)])
+ (parallel
+ [(set (match_operand:DI 2 "register_operand" "=r,r,r")
+ (plus:DI (match_operand:DI 3 "register_operand" "%r,r,a")
+ (match_operand:DI 4 "gr_reg_or_22bit_operand" "r,I,J")))
+ (set (match_operand:DI 5 "register_operand" "+r,r,r")
+ (match_dup 5))]))]
+ ""
+ "@
+ (%J0) add %2 = %3, %4
+ (%J0) adds %2 = %3, %4
+ (%J0) addl %2 = %3, %4"
+ [(set_attr "itanium_class" "ialu")
+ (set_attr "predicable" "no")])