Revert "skip broken test" programmerjake/readd-rhs-copy
authorJacob Lifshay <programmerjake@gmail.com>
Fri, 20 Oct 2023 01:57:00 +0000 (18:57 -0700)
committerJacob Lifshay <programmerjake@gmail.com>
Tue, 24 Oct 2023 00:15:17 +0000 (17:15 -0700)
requested by luke:
https://bugs.libre-soc.org/show_bug.cgi?id=1193#c1

This reverts commit e0a4f19b2c90be84a77a4aa584c6d60e508d92f5.

src/openpower/decoder/helpers.py
src/openpower/decoder/pseudo/parser.py
src/openpower/decoder/pseudo/pyfnwriter.py
src/openpower/decoder/pseudo/pywriter.py
src/openpower/test/trap/trap_cases.py

index 99131c7fdb5457e8bc7bf5232e686e7e035d950b..2c93713484dbde0da0c774db94ef518df70888a3 100644 (file)
@@ -72,6 +72,35 @@ def EXTS128(value):
     return SelectableInt(exts(value.value, value.bits) & ((1 << 128)-1), 128)
 
 
     return SelectableInt(exts(value.value, value.bits) & ((1 << 128)-1), 128)
 
 
+def copy_assign_rhs(inp):
+    """ implicitly added function call to all assignment RHSes.
+        This copies the passed-in value so later assignments to parts of the
+        LHS don't modify the RHS if it's a SelectableInt.
+
+        Example:
+        ```
+        # this needs to copy the SelectableInt instance in RA
+        # not just assign a reference to it to A
+        A <- RA
+        A[0] <- 1  # if the copy wasn't performed, we just modified RA too!
+        ```
+    """
+    if isinstance(inp, (str, int)):
+        return inp
+    if isinstance(inp, (SelectableInt, FieldSelectableInt)):
+        return SelectableInt(inp)
+    if isinstance(inp, BFPState):
+        return BFPState(inp)
+    if isinstance(inp, SelectableMSB0Fraction):
+        return SelectableMSB0Fraction(inp)
+    if isinstance(inp, tuple):
+        return tuple(map(copy_assign_rhs, inp))
+    if isinstance(inp, dict):
+        return {copy_assign_rhs(k): copy_assign_rhs(v) for k, v in inp.items()}
+    raise TypeError("tried to assign an unsupported type in pseudo-code",
+                    repr(type(inp)))
+
+
 # signed version of MUL
 def MULS(a, b):
     if isinstance(b, int):
 # signed version of MUL
 def MULS(a, b):
     if isinstance(b, int):
index 6a94e701e8b2e2b937fa84aa8e0b1161b2465fb8..8e9132447ed8207875dc4058d4919ea14d207634 100644 (file)
@@ -405,7 +405,12 @@ class PowerParser:
                     self.read_regs.add(toname)
             if name and name in self.gprs:
                 self.write_regs.add(name)  # add to list of regs to write
                     self.read_regs.add(toname)
             if name and name in self.gprs:
                 self.write_regs.add(name)  # add to list of regs to write
-            p[0] = self.Assign(autoassign, name, p[1], p[3], iea_mode,
+
+            # copy rhs -- see openpower.decoder.helpers.copy_assign_rhs()'s
+            # documentation for why we need this
+            copy_fn = ast.Name("copy_assign_rhs", ast.Load())
+            rhs = ast.Call(copy_fn, (p[3],), [])
+            p[0] = self.Assign(autoassign, name, p[1], rhs, iea_mode,
                                p.slice[2])
             if name:
                 self.declared_vars.add(name)
                                p.slice[2])
             if name:
                 self.declared_vars.add(name)
index 448b3e345b89fae8bb33fb06df5d451ec5c748f6..417706a4df0af58f1be1af6c285998a3862a607e 100644 (file)
@@ -21,7 +21,7 @@ header = """\
 from openpower.decoder.isa.caller import inject
 from openpower.decoder.helpers import (ISACallerHelper,
                                  ne, eq, gt, ge, lt, le, ltu, gtu, length,
 from openpower.decoder.isa.caller import inject
 from openpower.decoder.helpers import (ISACallerHelper,
                                  ne, eq, gt, ge, lt, le, ltu, gtu, length,
-                                 trunc_divs, trunc_rems,
+                                 trunc_divs, trunc_rems, copy_assign_rhs,
                                 )
 from openpower.decoder.selectable_int import SelectableInt
 from openpower.decoder.selectable_int import selectconcat as concat
                                 )
 from openpower.decoder.selectable_int import SelectableInt
 from openpower.decoder.selectable_int import selectconcat as concat
index b0772935a86ca6af4e1c1dd3d43d11f2783f28d0..6d436eef2f8f9877322bd6e91d2022f6c36a09b9 100644 (file)
@@ -23,7 +23,7 @@ header = """\
 from openpower.decoder.isa.caller import inject, instruction_info
 from openpower.decoder.helpers import (
                                  ne, eq, gt, ge, lt, le, ltu, gtu, length,
 from openpower.decoder.isa.caller import inject, instruction_info
 from openpower.decoder.helpers import (
                                  ne, eq, gt, ge, lt, le, ltu, gtu, length,
-                                 RANGE,
+                                 RANGE, copy_assign_rhs,
                                  ISACallerHelper,
                                 )
 from openpower.decoder.selectable_int import SelectableInt
                                  ISACallerHelper,
                                 )
 from openpower.decoder.selectable_int import SelectableInt
index 1e91eb8b7888ac8b33e55b832045d13046becc4d..b90bf6939fff94c027f99cc219517d89eec4748a 100644 (file)
@@ -8,7 +8,6 @@ import random
 
 
 class TrapTestCase(TestAccumulatorBase):
 
 
 class TrapTestCase(TestAccumulatorBase):
-
     def case_1_kaivb(self):
         # https://bugs.libre-soc.org/show_bug.cgi?id=859
         lst = ["mtspr 850, 1",  # KAIVB
     def case_1_kaivb(self):
         # https://bugs.libre-soc.org/show_bug.cgi?id=859
         lst = ["mtspr 850, 1",  # KAIVB
@@ -21,7 +20,7 @@ class TrapTestCase(TestAccumulatorBase):
         msr = 0xa000000000000003
         self.add_case(Program(lst, bigendian),
                       initial_regs, initial_sprs,
         msr = 0xa000000000000003
         self.add_case(Program(lst, bigendian),
                       initial_regs, initial_sprs,
-                                    initial_msr=msr)
+                      initial_msr=msr)
 
     def case_2_kaivb_test(self):
         # https://bugs.libre-soc.org/show_bug.cgi?id=859
 
     def case_2_kaivb_test(self):
         # https://bugs.libre-soc.org/show_bug.cgi?id=859
@@ -31,17 +30,20 @@ class TrapTestCase(TestAccumulatorBase):
                "tbegin.",       # deliberately use illegal instruction
                ]
         initial_regs = [0] * 32
                "tbegin.",       # deliberately use illegal instruction
                ]
         initial_regs = [0] * 32
-        initial_regs[1] = 1<<13
+        initial_regs[1] = 1 << 13
         initial_sprs = {'KAIVB': 0x12345678,
                         }
         msr = 0xa000000000000003
         e = ExpectedState(pc=0x2700)
         initial_sprs = {'KAIVB': 0x12345678,
                         }
         msr = 0xa000000000000003
         e = ExpectedState(pc=0x2700)
-        e.intregs[1] = 1<<13
-        e.msr = 0xa000000000000003 # TODO, not actually checked
+        e.intregs[1] = 1 << 13
+        e.sprs['SRR0'] = 0x4
+        e.sprs['SRR1'] = 0xa000000000080003
+        e.sprs['KAIVB'] = 0x2000
+        e.msr = 0xa000000000000001
         self.add_case(Program(lst, bigendian),
                       initial_regs, initial_sprs,
         self.add_case(Program(lst, bigendian),
                       initial_regs, initial_sprs,
-                                    initial_msr=msr,
-                                    expected=e)
+                      initial_msr=msr,
+                      expected=e)
 
     def case_0_hrfid(self):
         lst = ["hrfid"]
 
     def case_0_hrfid(self):
         lst = ["hrfid"]
@@ -55,12 +57,12 @@ class TrapTestCase(TestAccumulatorBase):
         lst = ["sc 0"]
         initial_regs = [0] * 32
         initial_regs[1] = 1
         lst = ["sc 0"]
         initial_regs = [0] * 32
         initial_regs[1] = 1
-        initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678} # to overwrite
+        initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678}  # to overwrite
         # expected results: PC should be at 0xc00 (sc address)
         e = ExpectedState(pc=0xc00)
         e.intregs[1] = 1
         e.sprs['SRR0'] = 4                  # PC to return to: CIA+4
         # expected results: PC should be at 0xc00 (sc address)
         e = ExpectedState(pc=0xc00)
         e.intregs[1] = 1
         e.sprs['SRR0'] = 4                  # PC to return to: CIA+4
-        e.sprs['SRR1'] = 0x9000000000022903 # MSR to restore after sc return
+        e.sprs['SRR1'] = 0x9000000000022903  # MSR to restore after sc return
         e.msr = 0x9000000000000001          # MSR changed to this by sc/trap
         self.add_case(Program(lst, bigendian),
                       initial_regs, initial_sprs,
         e.msr = 0x9000000000000001          # MSR changed to this by sc/trap
         self.add_case(Program(lst, bigendian),
                       initial_regs, initial_sprs,
@@ -107,11 +109,11 @@ class TrapTestCase(TestAccumulatorBase):
         initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0xb000000000001033}
         e = ExpectedState(pc=0x700)
         e.intregs[1] = 1
         initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0xb000000000001033}
         e = ExpectedState(pc=0x700)
         e.intregs[1] = 1
-        e.msr = 0xb000000000001033 # TODO, not actually checked
+        e.msr = 0xb000000000001033  # TODO, not actually checked
         self.add_case(Program(lst, bigendian),
                       initial_regs, initial_sprs,
         self.add_case(Program(lst, bigendian),
                       initial_regs, initial_sprs,
-                                    initial_msr=0xa000000000000003,
-                                    expected=e)
+                      initial_msr=0xa000000000000003,
+                      expected=e)
 
     def case_0_trap_eq_imm(self):
         insns = ["twi", "tdi"]
 
     def case_0_trap_eq_imm(self):
         insns = ["twi", "tdi"]
@@ -149,7 +151,7 @@ class TrapTestCase(TestAccumulatorBase):
         initial_regs = [0] * 32
         initial_regs[1] = 0xb000000000001033
         self.add_case(Program(lst, bigendian), initial_regs,
         initial_regs = [0] * 32
         initial_regs[1] = 0xb000000000001033
         self.add_case(Program(lst, bigendian), initial_regs,
-                                    initial_msr=0xa000000000000003)
+                      initial_msr=0xa000000000000003)
 
     def case_4_mtmsrd_0(self):
         lst = ["mtmsrd 1,0"]
 
     def case_4_mtmsrd_0(self):
         lst = ["mtmsrd 1,0"]
@@ -202,4 +204,3 @@ class TrapTestCase(TestAccumulatorBase):
                "mtmsr 1,1"]  # should not get executed
         initial_regs = [0] * 32
         self.add_case(Program(lst, bigendian), initial_regs)
                "mtmsr 1,1"]  # should not get executed
         initial_regs = [0] * 32
         self.add_case(Program(lst, bigendian), initial_regs)
-