projects
/
litex.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
|
inline
| side by side (parent:
6b7ca0c
)
cores/clock/s6pll: add phase support
author
Florent Kermarrec
<florent@enjoy-digital.fr>
Wed, 7 Aug 2019 06:18:54 +0000
(08:18 +0200)
committer
Florent Kermarrec
<florent@enjoy-digital.fr>
Wed, 7 Aug 2019 06:18:54 +0000
(08:18 +0200)
litex/soc/cores/clock.py
patch
|
blob
|
history
diff --git
a/litex/soc/cores/clock.py
b/litex/soc/cores/clock.py
index ed07b8716c34b892bb2bebbac2d2bc1c41f8d0f5..0c21251713252eb2def23fd6973afc6e862d8396 100644
(file)
--- a/
litex/soc/cores/clock.py
+++ b/
litex/soc/cores/clock.py
@@
-143,9
+143,13
@@
class S6PLL(XilinxClocking):
pll_fb = Signal()
self.params.update(
p_SIM_DEVICE="SPARTAN6",
pll_fb = Signal()
self.params.update(
p_SIM_DEVICE="SPARTAN6",
+ p_BANDWIDTH="OPTIMIZED",
+ p_COMPENSATION="INTERNAL",
+ p_REF_JITTER=.01, p_CLK_FEEDBACK="CLKFBOUT",
p_CLKIN1_PERIOD=period_ns(self.clkin_freq),
p_CLKIN1_PERIOD=period_ns(self.clkin_freq),
- p_CLKIN2_PERIOD=
period_ns(self.clkin_freq)
,
+ p_CLKIN2_PERIOD=
0.
,
p_CLKFBOUT_MULT=config["clkfbout_mult"],
p_CLKFBOUT_MULT=config["clkfbout_mult"],
+ p_CLKFBOUT_PHASE=0.,
p_DIVCLK_DIVIDE=config["divclk_divide"],
i_CLKINSEL=1,
i_RST=self.reset,
p_DIVCLK_DIVIDE=config["divclk_divide"],
i_CLKINSEL=1,
i_RST=self.reset,
@@
-156,7
+160,8
@@
class S6PLL(XilinxClocking):
)
for n, (clk, f, p, m) in sorted(self.clkouts.items()):
self.params["p_CLKOUT{}_DIVIDE".format(n)] = config["clkout{}_divide".format(n)]
)
for n, (clk, f, p, m) in sorted(self.clkouts.items()):
self.params["p_CLKOUT{}_DIVIDE".format(n)] = config["clkout{}_divide".format(n)]
- self.params["p_CLKOUT{}_PHASE".format(n)] = config["clkout{}_phase".format(n)]
+ self.params["p_CLKOUT{}_PHASE".format(n)] = float(config["clkout{}_phase".format(n)])
+ self.params["p_CLKOUT{}_DUTY_CYCLE".format(n)] = 0.5
self.params["o_CLKOUT{}".format(n)] = clk
self.specials += Instance("PLL_ADV", **self.params)
self.params["o_CLKOUT{}".format(n)] = clk
self.specials += Instance("PLL_ADV", **self.params)