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Add simcells.v, simlib.v, and some output
author
Eddie Hung
<eddie@fpgeh.com>
Thu, 27 Jun 2019 18:13:49 +0000
(11:13 -0700)
committer
Eddie Hung
<eddie@fpgeh.com>
Thu, 27 Jun 2019 18:13:49 +0000
(11:13 -0700)
tests/arch/run-test.sh
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diff --git
a/tests/arch/run-test.sh
b/tests/arch/run-test.sh
index fc4175be88ae62a4d8b04ad5e05f402697258943..5292d161556509c91149ba26c3cece72ac0d5046 100755
(executable)
--- a/
tests/arch/run-test.sh
+++ b/
tests/arch/run-test.sh
@@
-4,5
+4,15
@@
set -e
echo "Running syntax check on arch sim models"
for arch in ../../techlibs/*; do
echo "Running syntax check on arch sim models"
for arch in ../../techlibs/*; do
- find $arch -name cells_sim.v -print0 | xargs -0 -n1 -r iverilog -t null -I$arch
+ find $arch -name cells_sim.v | while read path; do
+ echo -n "Test $path ->"
+ iverilog -t null -I$arch $path
+ echo " ok"
+ done
+done
+
+for path in "../../techlibs/common/simcells.v" "../../techlibs/common/simlib.v"; do
+ echo -n "Test $path ->"
+ iverilog -t null $path
+ echo " ok"
done
done