Similar to the changes already applied to Xilinx backend.
def add_period_constraint(self, platform, clk, period):
clk.attr.add("keep")
def add_period_constraint(self, platform, clk, period):
clk.attr.add("keep")
+ period = math.floor(period*1e3)/1e3 # round to lowest picosecond
- raise ValueError("A period constraint already exists")
- period = math.floor(period*1e3)/1e3 # Round to lowest picosecond
+ if period != self.clocks[clk]:
+ raise ValueError("Clock already constrained to {:.2f}ns, new constraint to {:.2f}ns"
+ .format(self.clocks[clk], period))
self.clocks[clk] = period
def add_false_path_constraint(self, platform, from_, to):
self.clocks[clk] = period
def add_false_path_constraint(self, platform, from_, to):