'K_MOD_EQ', 'K_AND_EQ', 'K_OR_EQ'),
('right', 'K_XOR_EQ', 'K_LS_EQ', 'K_RS_EQ', 'K_RSS_EQ'),
('right', '?', ':', 'K_inside'),
'K_MOD_EQ', 'K_AND_EQ', 'K_OR_EQ'),
('right', 'K_XOR_EQ', 'K_LS_EQ', 'K_RS_EQ', 'K_RSS_EQ'),
('right', '?', ':', 'K_inside'),
- ('left', 'K_LOR'),
- ('left', 'K_LAND'),
- ('left', '|'),
- ('left', '^', 'K_NXOR', 'K_NOR'),
- ('left', '&', 'K_NAND'),
- ('left', 'K_EQ', 'K_NE', 'K_CEQ', 'K_CNE', 'K_WEQ', 'K_WNE'),
- ('left', 'K_GE', 'K_LE', '<', '>'),
- ('left', 'K_LS', 'K_RS', 'K_RSS'),
- ('left', '+', '-'),
- ('left', '*', '/', '%'),
- ('left', 'K_POW'),
- ('left', 'UNARY_PREC'),
- ('nonassoc', 'less_than_K_else'),
- ('nonassoc', 'K_else'),
- ('nonassoc', '('),
- ('nonassoc', 'K_exclude'),
- ('nonassoc', 'no_timeunits_declaration'),
- ('nonassoc', 'one_timeunits_declaration'),
+ ('left', 'K_LOR'),
+ ('left', 'K_LAND'),
+ ('left', '|'),
+ ('left', '^', 'K_NXOR', 'K_NOR'),
+ ('left', '&', 'K_NAND'),
+ ('left', 'K_EQ', 'K_NE', 'K_CEQ', 'K_CNE', 'K_WEQ', 'K_WNE'),
+ ('left', 'K_GE', 'K_LE', '<', '>'),
+ ('left', 'K_LS', 'K_RS', 'K_RSS'),
+ ('left', '+', '-'),
+ ('left', '*', '/', '%'),
+ ('left', 'K_POW'),
+ ('left', 'UNARY_PREC'),
+ ('nonassoc', 'less_than_K_else'),
+ ('nonassoc', 'K_else'),
+ ('nonassoc', '('),
+ ('nonassoc', 'K_exclude'),
+ ('nonassoc', 'no_timeunits_declaration'),
+ ('nonassoc', 'one_timeunits_declaration'),
+"""
+ IVL_VT_VOID = 0, /* Not used */
+ IVL_VT_NO_TYPE = 1, /* Place holder for missing/unknown type. */
+ IVL_VT_REAL = 2,
+ IVL_VT_BOOL = 3,
+ IVL_VT_LOGIC = 4,
+ IVL_VT_STRING = 5,
+ IVL_VT_DARRAY = 6, /* Array (esp. dynamic array) */
+ IVL_VT_CLASS = 7, /* SystemVerilog class instances */
+ IVL_VT_QUEUE = 8, /* SystemVerilog queue instances */
+ IVL_VT_VECTOR = IVL_VT_LOGIC /* For compatibility */
+"""
+def indent(s, i=4):
+ st = ''
+ for x in s:
+ st += str(x)
+ res = []
+ for p in st.split('\n'):
+ res.append(' ' * i + p)
+ return '\n'.join(res)
+
+
+class DataType:
+ def __init__(self, typ, signed):
+ self.typ = typ
+ self.signed = signed
+
+def port_decl(comment, dt, name):
+ if dt.dims is None:
+ width = '' # width: 1
+ else:
+ width = dt.dims
+ # XXX TODO, better checking, should be using data structure... *sigh*
+ width = width[1:-1] # strip brackets
+ width = width.split(':')
+ assert width[0] == '0'
+ width = width[1]
+ return 'self.%s = Signal(%s) # %s' % (name, width, comment)
# PForStatement*tmp_for = new PForStatement(tmp_ident, $6, $8, $10, $13);
# FILE_NAME(tmp_for, @1);
# PForStatement*tmp_for = new PForStatement(tmp_ident, $6, $8, $10, $13);
# FILE_NAME(tmp_for, @1);
'''loop_statement : K_foreach '(' IDENTIFIER '[' loop_variables ']' ')' _embed1_loop_statement statement_or_null '''
print('loop_statement_7', list(p))
# { PForeach*tmp_for = pform_make_foreach(@1, $3, $5, $9);
'''loop_statement : K_foreach '(' IDENTIFIER '[' loop_variables ']' ')' _embed1_loop_statement statement_or_null '''
print('loop_statement_7', list(p))
# { PForeach*tmp_for = pform_make_foreach(@1, $3, $5, $9);
# { perm_string name = lex_strings.make($3.text);
# if (pform_test_type_identifier_local(name)) {
# yyerror(@3, "error: Typedef identifier \"%s\" is already a type name.", $3.text);
# { perm_string name = lex_strings.make($3.text);
# if (pform_test_type_identifier_local(name)) {
# yyerror(@3, "error: Typedef identifier \"%s\" is already a type name.", $3.text);
def p_list_of_port_declarations_2(p):
'''list_of_port_declarations : list_of_port_declarations ',' port_declaration '''
print('list_of_port_declarations_2', list(p))
def p_list_of_port_declarations_2(p):
'''list_of_port_declarations : list_of_port_declarations ',' port_declaration '''
print('list_of_port_declarations_2', list(p))
'''module_parameter_port_list : module_parameter_port_list ',' K_parameter param_type parameter_assign '''
print('module_parameter_port_list_3', list(p))
p[1].append(Leaf(token.COMMA, ','))
'''module_parameter_port_list : module_parameter_port_list ',' K_parameter param_type parameter_assign '''
print('module_parameter_port_list_3', list(p))
p[1].append(Leaf(token.COMMA, ','))