projects
/
sifive-blocks.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
|
inline
| side by side (parent:
7c11879
)
GPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they...
author
Megan Wachs
<megan@sifive.com>
Tue, 13 Jun 2017 00:53:51 +0000
(17:53 -0700)
committer
Megan Wachs
<megan@sifive.com>
Tue, 13 Jun 2017 00:53:51 +0000
(17:53 -0700)
src/main/scala/devices/i2c/I2CPeriphery.scala
patch
|
blob
|
history
src/main/scala/devices/spi/SPIPeriphery.scala
patch
|
blob
|
history
src/main/scala/devices/uart/UARTPeriphery.scala
patch
|
blob
|
history
diff --git
a/src/main/scala/devices/i2c/I2CPeriphery.scala
b/src/main/scala/devices/i2c/I2CPeriphery.scala
index a79f94c5588af415ad3797aad6409830e9b802dc..d9c3ff4085d3aa515f1dcc309dd6eed5d77d8002 100644
(file)
--- a/
src/main/scala/devices/i2c/I2CPeriphery.scala
+++ b/
src/main/scala/devices/i2c/I2CPeriphery.scala
@@
-22,8
+22,8
@@
trait HasPeripheryI2C extends HasSystemNetworks {
trait HasPeripheryI2CBundle {
val i2cs: Vec[I2CPort]
trait HasPeripheryI2CBundle {
val i2cs: Vec[I2CPort]
- def toGPIOPins(
dummy: Int = 1
): Seq[I2CGPIOPort] = i2cs.map { i =>
- val pin = Module(new I2CGPIOPort)
+ def toGPIOPins(
syncStages: Int = 0
): Seq[I2CGPIOPort] = i2cs.map { i =>
+ val pin = Module(new I2CGPIOPort
(syncStages)
)
pin.io.i2c <> i
pin
}
pin.io.i2c <> i
pin
}
diff --git
a/src/main/scala/devices/spi/SPIPeriphery.scala
b/src/main/scala/devices/spi/SPIPeriphery.scala
index bd77259dad2577e205c3e13b371c0699f88c14c2..4361b1a1561dd922fa6cff8dc364dafb507d5dbe 100644
(file)
--- a/
src/main/scala/devices/spi/SPIPeriphery.scala
+++ b/
src/main/scala/devices/spi/SPIPeriphery.scala
@@
-23,8
+23,8
@@
trait HasPeripherySPI extends HasSystemNetworks {
trait HasPeripherySPIBundle {
val spis: HeterogeneousBag[SPIPortIO]
trait HasPeripherySPIBundle {
val spis: HeterogeneousBag[SPIPortIO]
- def SPItoGPIOPins(sync
_s
tages: Int = 0): Seq[SPIGPIOPort] = spis.map { s =>
- val pin = Module(new SPIGPIOPort(s.c, sync
_s
tages))
+ def SPItoGPIOPins(sync
S
tages: Int = 0): Seq[SPIGPIOPort] = spis.map { s =>
+ val pin = Module(new SPIGPIOPort(s.c, sync
S
tages))
pin.io.spi <> s
pin
}
pin.io.spi <> s
pin
}
diff --git
a/src/main/scala/devices/uart/UARTPeriphery.scala
b/src/main/scala/devices/uart/UARTPeriphery.scala
index 05c4a33890e13280f646b40cd5f242ad599f82b6..1f8011ee5e6cb8967689a01a46db5d3984495409 100644
(file)
--- a/
src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/
src/main/scala/devices/uart/UARTPeriphery.scala
@@
-29,8
+29,8
@@
trait HasPeripheryUARTBundle {
uarts.foreach { _.rxd := UInt(1) }
}
uarts.foreach { _.rxd := UInt(1) }
}
- def UARTtoGPIOPins(sync
_s
tages: Int = 0): Seq[UARTGPIOPort] = uarts.map { u =>
- val pin = Module(new UARTGPIOPort(sync
_s
tages))
+ def UARTtoGPIOPins(sync
S
tages: Int = 0): Seq[UARTGPIOPort] = uarts.map { u =>
+ val pin = Module(new UARTGPIOPort(sync
S
tages))
pin.io.uart <> u
pin
}
pin.io.uart <> u
pin
}