converted test_caller_svstate.py to new reg format

https://bugs.libre-soc.org/show_bug.cgi?id=884#c0

diff --git a/src/openpower/decoder/isa/test_caller_svstate.py b/src/openpower/decoder/isa/test_caller_svstate.py
index e228b8ce4b4f80cf68db0e30ac89e24062bcb4ea..5ba0f77f75e15f6ad4d8d352fcc31e783a6b1cdb 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svstate.py
+++ b/src/openpower/decoder/isa/test_caller_svstate.py
@@ -35,7 +35,7 @@ class SVSTATETestCase(FHDLTestCase):
             because whilst the Vector instruction was moved on by srcstep,
             the Scalar one is NOT moved on.
         """
             because whilst the Vector instruction was moved on by srcstep,
             the Scalar one is NOT moved on.
         """

-        isa = SVP64Asm(['sv.add 1, 5.v, 9.v'
+        isa = SVP64Asm(['sv.add 1, *5, *9'

                        ])
         lst = list(isa)
         print ("listing", lst)
                        ])
         lst = list(isa)
         print ("listing", lst)


@@ -66,11 +66,11 @@ class SVSTATETestCase(FHDLTestCase):
     def test_svstep_add_1(self):
         """tests svstep with an add, using scalar adds, when it reaches VL
         lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",
     def test_svstep_add_1(self):
         """tests svstep with an add, using scalar adds, when it reaches VL
         lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",

-                        'sv.add 1, 5.v, 9.v',
-                        'sv.addi 12.v, 1, 1',
+                        'sv.add 1, *5, *9',
+                        'sv.addi *12, 1, 1',

                         "setvl. 0, 0, 1, 1, 0, 0",
                         "setvl. 0, 0, 1, 1, 0, 0",

-                        'sv.add 1, 5.v, 9.v',
-                        'sv.addi 12.v, 1, 1',
+                        'sv.add 1, *5, *9',
+                        'sv.addi *12, 1, 1',

                         "setvl. 0, 0, 1, 1, 0, 0"
                         ])
 
                         "setvl. 0, 0, 1, 1, 0, 0"
                         ])
 


@@ -98,11 +98,11 @@ class SVSTATETestCase(FHDLTestCase):
 
         """
         lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",
 
         """
         lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",

-                        'sv.add 1, 5.v, 9.v',       # scalar dest (into r1)
-                        'sv.addi 12.v, 1, 1',       # scalar src (from r1)
+                        'sv.add 1, *5, *9',       # scalar dest (into r1)
+                        'sv.addi *12, 1, 1',       # scalar src (from r1)

                         "setvl. 0, 0, 1, 1, 0, 0",  # svstep
                         "setvl. 0, 0, 1, 1, 0, 0",  # svstep

-                        'sv.add 1, 5.v, 9.v',       # again, scalar dest
-                        'sv.addi 12.v, 1, 1',       # but vector dest
+                        'sv.add 1, *5, *9',       # again, scalar dest
+                        'sv.addi *12, 1, 1',       # but vector dest

                         "setvl. 0, 0, 1, 1, 0, 0"  # svstep (end: sets CR0.SO)
                         ])
         lst = list(lst)
                         "setvl. 0, 0, 1, 1, 0, 0"  # svstep (end: sets CR0.SO)
                         ])
         lst = list(lst)