Fix a commit
b015e599c772 ("[MIPS] Add new virtualization instructions"),
<https://sourceware.org/ml/binutils/2013-05/msg00118.html>, regression
and bring the disassembly of the RFE instruction back for the relevant
ISA levels.
It is because the "rfe" opcode table entry was incorrectly moved behind
the catch-all generic "c0" entry for CP0 instructions, causing output
like:
00:
42000010 c0 0x10
to be produced rather than:
00:
42000010 rfe
even for ISA levels that do include the RFE instruction.
Move the "rfe" entry ahead of "c0" then, correcting the problem. Add a
suitable test case.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
of "c0".
gas/
* testsuite/gas/mips/rfe.d: New test.
* testsuite/gas/mips/rfe.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
+2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
+
+ * testsuite/gas/mips/rfe.d: New test.
+ * testsuite/gas/mips/rfe.s: New test source.
+ * testsuite/gas/mips/mips.exp: Run the new test.
+
2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
* testsuite/gas/mips/cp1-names-r3900.d: New test.
2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
* testsuite/gas/mips/cp1-names-r3900.d: New test.
run_dump_test_arches "cp0m" [mips_arch_list_matching mips1 \
!mips2 !micromips]
run_dump_test_arches "cp0m" [mips_arch_list_matching mips1 \
!mips2 !micromips]
+ run_dump_test_arches "rfe" [mips_arch_list_matching mips1 \
+ !mips3 !mips32 !micromips]
+
run_dump_test "cp1-names-numeric"
run_dump_test "cp1-names-r3000"
run_dump_test "cp1-names-r3900"
run_dump_test "cp1-names-numeric"
run_dump_test "cp1-names-r3000"
run_dump_test "cp1-names-r3900"
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS RFE instruction
+#as: -32
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 42000010 rfe
+ \.\.\.
--- /dev/null
+ .text
+ .set noreorder
+foo:
+ rfe
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
+2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
+
+ * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
+ of "c0".
+
2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
* mips-dis.c (mips_cp1_names_mips): New variable.
2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
* mips-dis.c (mips_cp1_names_mips): New variable.
{"ginvi", "s", 0x7c00003d, 0xfc1fffff, RD_1, 0, 0, GINV, 0 },
{"ginvt", "s,+\\", 0x7c0000bd, 0xfc1ffcff, RD_1, 0, 0, GINV, 0 },
{"ginvi", "s", 0x7c00003d, 0xfc1fffff, RD_1, 0, 0, GINV, 0 },
{"ginvt", "s,+\\", 0x7c0000bd, 0xfc1ffcff, RD_1, 0, 0, GINV, 0 },
+/* RFE conflicts with the new Virt spec instruction tlbgp. */
+{"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3, 0, 0 },
+
/* No hazard protection on coprocessor instructions--they shouldn't
change the state of the processor and if they do it's up to the
user to put in nops as necessary. These are at the end so that the
/* No hazard protection on coprocessor instructions--they shouldn't
change the state of the processor and if they do it's up to the
user to put in nops as necessary. These are at the end so that the
{"cop1", "C", 0, (int) M_COP1, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 },
{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 },
{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 },
{"cop1", "C", 0, (int) M_COP1, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 },
{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 },
{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 },
-/* RFE conflicts with the new Virt spec instruction tlbgp. */
-{"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3, 0, 0 },
};
#define MIPS_NUM_OPCODES \
};
#define MIPS_NUM_OPCODES \