- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
-
- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL);
-
- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL);
-
- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL);
-
- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
-
- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, 0xFFFFFFFF, NULL);
-
- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONFIG, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
+
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONFIG, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONFIG, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL);
+
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL);
+
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONFIG, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL);
+
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
+
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, 0xFFFFFFFF, NULL);
+
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONFIG, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL);
+
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL);
+
+r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028810_PA_CL_CLIP_CNTL,
+ 0x0, 0xFFFFFFFF, NULL);
+