(no commit message)

diff --git a/docs/pinmux.mdwn b/docs/pinmux.mdwn
index 12b81385798ed9a523f3f17738d9badb2f33025d..d51b49b905d97954719d5eceede0658df8b7813a 100644 (file)
--- a/docs/pinmux.mdwn
+++ b/docs/pinmux.mdwn
@@ -2,7 +2,11 @@
 
 Managing IO on an ASIC is nowhere near as simple as on an FPGA.
 An FPGA has built-in IO Pads, the wires terminate inside an
 
 Managing IO on an ASIC is nowhere near as simple as on an FPGA.
 An FPGA has built-in IO Pads, the wires terminate inside an

-existing silicon block which has been tested for you.
+existing silicon block which has been tested for you.  In an
+ASIC, a bi-directional IO Pad requires three wires (in, out,
+out-enable) to be routed right the way from the ASIC, all
+the way to the IO PAD, where only then does a wire bond connect
+it to a single pin.

 
 Designing an ASIC, there is no guarantee that the IO pad is
 working when manufactured. Worse, the peripheral could be
 
 Designing an ASIC, there is no guarantee that the IO pad is
 working when manufactured. Worse, the peripheral could be