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sifive-blocks: trust diplomacy to get names right
author
Wesley W. Terpstra
<wesley@sifive.com>
Wed, 1 Feb 2017 21:53:54 +0000
(13:53 -0800)
committer
Wesley W. Terpstra
<wesley@sifive.com>
Wed, 1 Feb 2017 21:53:54 +0000
(13:53 -0800)
src/main/scala/devices/pwm/PWMPeriphery.scala
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src/main/scala/devices/spi/SPIPeriphery.scala
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src/main/scala/devices/uart/UARTPeriphery.scala
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diff --git
a/src/main/scala/devices/pwm/PWMPeriphery.scala
b/src/main/scala/devices/pwm/PWMPeriphery.scala
index 992699fa6c907e949a3e168eb7913787ed02b0bd..86e9ad2f3f8756aca2db7300190f28131faf0497 100644
(file)
--- a/
src/main/scala/devices/pwm/PWMPeriphery.scala
+++ b/
src/main/scala/devices/pwm/PWMPeriphery.scala
@@
-30,8
+30,8
@@
class PWMGPIOPort(c: PWMBundleConfig)(implicit p: Parameters) extends Module {
trait PeripheryPWM {
this: TopNetwork { val pwmConfigs: Seq[PWMConfig] } =>
trait PeripheryPWM {
this: TopNetwork { val pwmConfigs: Seq[PWMConfig] } =>
- val pwm
Devices
= (pwmConfigs.zipWithIndex) map { case (c, i) =>
- val pwm = LazyModule(new TLPWM(c)
{ override lazy val valName = Some(s"pwm$i") }
)
+ val pwm = (pwmConfigs.zipWithIndex) map { case (c, i) =>
+ val pwm = LazyModule(new TLPWM(c))
pwm.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
intBus.intnode := pwm.intnode
pwm
pwm.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
intBus.intnode := pwm.intnode
pwm
@@
-52,7
+52,7
@@
trait PeripheryPWMModule {
val outer: PeripheryPWM
val io: PeripheryPWMBundle
} =>
val outer: PeripheryPWM
val io: PeripheryPWMBundle
} =>
- (io.pwms.zipWithIndex zip outer.pwm
Devices
) foreach { case ((io, i), device) =>
+ (io.pwms.zipWithIndex zip outer.pwm) foreach { case ((io, i), device) =>
io.port := device.module.io.gpio
}
}
io.port := device.module.io.gpio
}
}
diff --git
a/src/main/scala/devices/spi/SPIPeriphery.scala
b/src/main/scala/devices/spi/SPIPeriphery.scala
index 40bcec692f9265f5b9fa590a09a060194244ff23..f4773a228c7cabf9646381ed4b9cea756be77270 100644
(file)
--- a/
src/main/scala/devices/spi/SPIPeriphery.scala
+++ b/
src/main/scala/devices/spi/SPIPeriphery.scala
@@
-8,8
+8,8
@@
import rocketchip.{TopNetwork,TopNetworkModule}
trait PeripherySPI {
this: TopNetwork { val spiConfigs: Seq[SPIConfig] } =>
trait PeripherySPI {
this: TopNetwork { val spiConfigs: Seq[SPIConfig] } =>
- val spi
Devices
= (spiConfigs.zipWithIndex) map {case (c, i) =>
- val spi = LazyModule(new TLSPI(c)
{ override lazy val valName = Some(s"spi$i") }
)
+ val spi = (spiConfigs.zipWithIndex) map {case (c, i) =>
+ val spi = LazyModule(new TLSPI(c))
spi.rnode := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
intBus.intnode := spi.intnode
spi
spi.rnode := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
intBus.intnode := spi.intnode
spi
@@
-28,7
+28,7
@@
trait PeripherySPIModule {
val outer: PeripherySPI
val io: PeripherySPIBundle
} =>
val outer: PeripherySPI
val io: PeripherySPIBundle
} =>
- (io.spis zip outer.spi
Devices
).foreach { case (io, device) =>
+ (io.spis zip outer.spi).foreach { case (io, device) =>
io <> device.module.io.port
}
}
io <> device.module.io.port
}
}
diff --git
a/src/main/scala/devices/uart/UARTPeriphery.scala
b/src/main/scala/devices/uart/UARTPeriphery.scala
index fd5bc35db4838105187197ef82622c31c948a2d1..3639d9baebef5c5ad1e5541e62f1a9e679ae52aa 100644
(file)
--- a/
src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/
src/main/scala/devices/uart/UARTPeriphery.scala
@@
-14,8
+14,8
@@
trait PeripheryUART {
this: TopNetwork {
val uartConfigs: Seq[UARTConfig]
} =>
this: TopNetwork {
val uartConfigs: Seq[UARTConfig]
} =>
- val uart
Devices
= uartConfigs.zipWithIndex.map { case (c, i) =>
- val uart = LazyModule(new UART(c)
{ override lazy val valName = Some(s"uart$i") }
)
+ val uart = uartConfigs.zipWithIndex.map { case (c, i) =>
+ val uart = LazyModule(new UART(c))
uart.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
intBus.intnode := uart.intnode
uart
uart.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
intBus.intnode := uart.intnode
uart
@@
-32,7
+32,7
@@
trait PeripheryUARTModule {
val outer: PeripheryUART
val io: PeripheryUARTBundle
} =>
val outer: PeripheryUART
val io: PeripheryUARTBundle
} =>
- (io.uarts zip outer.uart
Devices
).foreach { case (io, device) =>
+ (io.uarts zip outer.uart).foreach { case (io, device) =>
io <> device.module.io.port
}
}
io <> device.module.io.port
}
}