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Expand dirty-bit test to test MPRV and SUM
author
Andrew Waterman
<andrew@sifive.com>
Thu, 30 Mar 2017 07:30:29 +0000
(
00:30
-0700)
committer
Andrew Waterman
<andrew@sifive.com>
Thu, 30 Mar 2017 07:30:29 +0000
(
00:30
-0700)
isa/rv64si/dirty.S
patch
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diff --git
a/isa/rv64si/dirty.S
b/isa/rv64si/dirty.S
index 86e4656059fb8ae395607c55c8c281a096d5bb07..17aa57f7145c67563d891772132f763d8a2e2205 100644
(file)
--- a/
isa/rv64si/dirty.S
+++ b/
isa/rv64si/dirty.S
@@
-13,40
+13,45
@@
RVTEST_RV64M
RVTEST_CODE_BEGIN
RVTEST_RV64M
RVTEST_CODE_BEGIN
- # Turn on VM
with superpage identity mapping
+ # Turn on VM
li a0, (SPTBR_MODE & ~(SPTBR_MODE<<1)) * SPTBR_MODE_SV39
la a1, page_table_1
srl a1, a1, RISCV_PGSHIFT
or a1, a1, a0
li a0, (SPTBR_MODE & ~(SPTBR_MODE<<1)) * SPTBR_MODE_SV39
la a1, page_table_1
srl a1, a1, RISCV_PGSHIFT
or a1, a1, a0
- la a2, page_table_2
- srl a2, a2, RISCV_PGSHIFT
- or a2, a2, a0
csrw sptbr, a1
sfence.vma
csrw sptbr, a1
sfence.vma
- li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_SUM
+
+ # Set up MPRV with MPP=S, so loads and stores use S-mode
+ li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_MPRV
csrs mstatus, a1
csrs mstatus, a1
- la a1, 1f - DRAM_BASE
- csrw mepc, a1
- la a1, stvec_handler - DRAM_BASE
- csrw stvec, a1
- mret
-1:
# Try a faulting store to make sure dirty bit is not set
li TESTNUM, 2
# Try a faulting store to make sure dirty bit is not set
li TESTNUM, 2
- li t
0
, 1
- sw t
0, dummy
, t1
+ li t
2
, 1
+ sw t
2, dummy - DRAM_BASE
, t1
- #
Load new page table
+ #
Set SUM=1 so user memory access is permitted
li TESTNUM, 3
li TESTNUM, 3
- csrw sptbr, a2
- sfence.vma
+ li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_SUM
+ csrs mstatus, a1
+
+ # Make sure SUM=1 works
+ lw t0, dummy - DRAM_BASE
+ bnez t0, die
# Try a non-faulting store to make sure dirty bit is set
# Try a non-faulting store to make sure dirty bit is set
- sw t0, dummy, t1
+ sw t2, dummy - DRAM_BASE, t1
+
+ # Make sure it succeeded
+ lw t0, dummy - DRAM_BASE
+ bne t0, t2, die
+
+ # Leave MPRV
+ li t0, MSTATUS_MPRV
+ csrc mstatus, t0
# Make sure D bit is set
# Make sure D bit is set
- lw t0, page_table_
2
+ lw t0, page_table_
1
li t1, PTE_A | PTE_D
and t0, t0, t1
bne t0, t1, die
li t1, PTE_A | PTE_D
and t0, t0, t1
bne t0, t1, die
@@
-56,8
+61,8
@@
RVTEST_CODE_BEGIN
TEST_PASSFAIL
.align 2
TEST_PASSFAIL
.align 2
-
s
tvec_handler:
- csrr t0,
s
cause
+
m
tvec_handler:
+ csrr t0,
m
cause
add t0, t0, -CAUSE_STORE_PAGE_FAULT
bnez t0, die
add t0, t0, -CAUSE_STORE_PAGE_FAULT
bnez t0, die
@@
-68,17
+73,17
@@
stvec_handler:
and t1, t0, PTE_D
bnez t1, die
skip:
and t1, t0, PTE_D
bnez t1, die
skip:
- csrr t0,
s
epc
+ csrr t0,
m
epc
add t0, t0, 4
add t0, t0, 4
- csrw
s
epc, t0
-
s
ret
+ csrw
m
epc, t0
+
m
ret
1:
li t1, 3
bne TESTNUM, t1, 1f
# The implementation doesn't appear to set D bits in HW. Skip the test,
# after making sure the D bit is clear.
1:
li t1, 3
bne TESTNUM, t1, 1f
# The implementation doesn't appear to set D bits in HW. Skip the test,
# after making sure the D bit is clear.
- lw t0, page_table_
2
+ lw t0, page_table_
1
and t1, t0, PTE_D
bnez t1, die
j pass
and t1, t0, PTE_D
bnez t1, die
j pass
@@
-95,9
+100,7
@@
RVTEST_DATA_BEGIN
TEST_DATA
.align 12
TEST_DATA
.align 12
-page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_X | PTE_A
+page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_
W | PTE_
X | PTE_A
dummy: .dword 0
dummy: .dword 0
-.align 12
-page_table_2: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_X | PTE_W | PTE_A
RVTEST_DATA_END
RVTEST_DATA_END