+static void simplemap_bu0(RTLIL::Module *module, RTLIL::Cell *cell)
+{
+ int width = cell->parameters.at("\\Y_WIDTH").as_int();
+
+ RTLIL::SigSpec sig_a = cell->connections.at("\\A");
+ sig_a.extend_u0(width, cell->parameters.at("\\A_SIGNED").as_bool());
+
+ RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
+
+ module->connections.push_back(RTLIL::SigSig(sig_y, sig_a));
+}
+