+"""SVP64 unit test for doing strange things to SVSTATE, manually.
+"""
+from nmigen import Module, Signal
+from nmigen.back.pysim import Simulator, Delay, Settle
+from nmutil.formaltest import FHDLTestCase
+import unittest
+from openpower.decoder.isa.caller import ISACaller
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.simulator.program import Program
+from openpower.decoder.isa.caller import ISACaller, SVP64State, CRFields
+from openpower.decoder.selectable_int import SelectableInt
+from openpower.decoder.orderedset import OrderedSet
+from openpower.decoder.isa.all import ISA
+from openpower.decoder.isa.test_caller import Register, run_tst
+from openpower.sv.trans.svp64 import SVP64Asm
+from openpower.consts import SVP64CROffs
+from copy import deepcopy
+
+
+class SVSTATETestCase(FHDLTestCase):
+
+ def _check_regs(self, sim, expected):
+ print ("GPR")
+ sim.gpr.dump()
+ for i in range(32):
+ self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
+
+ def test_sv_index(self):
+ """sets VL=2 (via SVSTATE) with a manual srcstep/dststep,
+ then does a scalar-result add. the result should be:
+
+ add 1, 6, 10
+
+ because whilst the Vector instruction was moved on by srcstep,
+ the Scalar one is NOT moved on.
+ """
+ isa = SVP64Asm(['svindex 1, 31, 5, 0, 0, 0, 0'
+ ])
+ lst = list(isa)
+ print ("listing", lst)
+
+ # initial values in GPR regfile
+ initial_regs = [0] * 32
+ initial_regs[9] = 0x1234
+ initial_regs[10] = 0x1111
+ initial_regs[5] = 0x4321
+ initial_regs[6] = 0x2223
+
+ # SVSTATE vl=10
+ svstate = SVP64State()
+ svstate.vl = 10 # VL
+ svstate.maxvl = 10 # MAXVL
+ print ("SVSTATE", bin(svstate.asint()))
+
+ # copy before running
+ expected_regs = deepcopy(initial_regs)
+ #expected_regs[1] = 0x3334
+
+ with Program(lst, bigendian=False) as program:
+ sim = self.run_tst_program(program, initial_regs, svstate=svstate)
+ self._check_regs(sim, expected_regs)
+
+ print ("SVSTATE after", bin(sim.svstate.asint()))
+ print (" vl", bin(sim.svstate.vl))
+ print (" mvl", bin(sim.svstate.maxvl))
+ print (" srcstep", bin(sim.svstate.srcstep))
+ print (" dststep", bin(sim.svstate.dststep))
+ print (" RMpst", bin(sim.svstate.RMpst))
+ print (" SVme", bin(sim.svstate.SVme))
+ print (" mo0", bin(sim.svstate.mo0))
+ print (" mo1", bin(sim.svstate.mo1))
+ print (" mi0", bin(sim.svstate.mi0))
+ print (" mi1", bin(sim.svstate.mi1))
+ print (" mi2", bin(sim.svstate.mi2))
+
+ def run_tst_program(self, prog, initial_regs=None,
+ svstate=None):
+ if initial_regs is None:
+ initial_regs = [0] * 32
+ simulator = run_tst(prog, initial_regs, svstate=svstate)
+ simulator.gpr.dump()
+ return simulator
+
+
+if __name__ == "__main__":
+ unittest.main()
+