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Fix typo and comments
author
Eddie Hung
<eddie@fpgeh.com>
Tue, 9 Jul 2019 17:38:07 +0000
(10:38 -0700)
committer
Eddie Hung
<eddie@fpgeh.com>
Tue, 9 Jul 2019 17:38:07 +0000
(10:38 -0700)
techlibs/xilinx/cells_map.v
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diff --git
a/techlibs/xilinx/cells_map.v
b/techlibs/xilinx/cells_map.v
index d3f6a60cc1f4bf5bd8cc612e5453971fdce62ffd..233a5600361e5e4de4dd8b823f3412422743b17b 100644
(file)
--- a/
techlibs/xilinx/cells_map.v
+++ b/
techlibs/xilinx/cells_map.v
@@
-204,7
+204,7
@@
module \$__XILINX_SHIFTX (A, B, Y);
end
else if (A_WIDTH <= 4) begin
// Rather than extend with 1'bx which gets flattened to 1'b0
end
else if (A_WIDTH <= 4) begin
// Rather than extend with 1'bx which gets flattened to 1'b0
- // causing the "don't care" status to get lost, extend with MSB
+ // causing the "don't care" status to get lost, extend with MSB
s
// so that we can recognise again later when mapping MUXF78
wire [4-1:0] Ax;
if (A_WIDTH == 4)
// so that we can recognise again later when mapping MUXF78
wire [4-1:0] Ax;
if (A_WIDTH == 4)
@@
-215,7
+215,7
@@
module \$__XILINX_SHIFTX (A, B, Y);
end
else if (A_WIDTH <= 8) begin
// Rather than extend with 1'bx which gets flattened to 1'b0
end
else if (A_WIDTH <= 8) begin
// Rather than extend with 1'bx which gets flattened to 1'b0
- // causing the "don't care" status to get lost, extend with MSB
+ // causing the "don't care" status to get lost, extend with MSB
s
// so that we can recognise again later when mapping MUXF78
wire [8-1:0] Ax;
if (A_WIDTH == 8)
// so that we can recognise again later when mapping MUXF78
wire [8-1:0] Ax;
if (A_WIDTH == 8)
@@
-230,13
+230,13
@@
module \$__XILINX_SHIFTX (A, B, Y);
end
else if (A_WIDTH <= 16) begin
// Rather than extend with 1'bx which gets flattened to 1'b0
end
else if (A_WIDTH <= 16) begin
// Rather than extend with 1'bx which gets flattened to 1'b0
- // causing the "don't care" status to get lost, extend with MSB
+ // causing the "don't care" status to get lost, extend with MSB
s
// so that we can recognise again later when mapping MUXF78
wire [16-1:0] Ax;
if (A_WIDTH == 16)
assign Ax = A;
else
// so that we can recognise again later when mapping MUXF78
wire [16-1:0] Ax;
if (A_WIDTH == 16)
assign Ax = A;
else
- assign Ax = {A[7-:
8
-A_WIDTH], A};
+ assign Ax = {A[7-:
16
-A_WIDTH], A};
wire T0 = B[2] ? B[3] ? Ax[12] : Ax[4]
: B[3] ? Ax[ 8] : Ax[0];
wire T1 = B[2] ? B[3] ? Ax[13] : Ax[5]
wire T0 = B[2] ? B[3] ? Ax[12] : Ax[4]
: B[3] ? Ax[ 8] : Ax[0];
wire T1 = B[2] ? B[3] ? Ax[13] : Ax[5]