(no commit message)

diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn
index afb375d0c30e55131c1362bccd5d26780d7d3157..16f8d4c0deb30490cb8a6a277741beff0e22dbc1 100644 (file)
--- a/openpower/sv/normal.mdwn
+++ b/openpower/sv/normal.mdwn
@@ -114,8 +114,9 @@ dest elwidth.
 Reduction in SVP64 is similar in essence to other Vector Processing
 ISAs, but leverages the underlying scalar Base v3.0B operations.
 Thus it is more a convention that the programmer may utilise to give
 Reduction in SVP64 is similar in essence to other Vector Processing
 ISAs, but leverages the underlying scalar Base v3.0B operations.
 Thus it is more a convention that the programmer may utilise to give

-the appearance and effect of a Horizontal Vector Reduction.
-Details are in the [[svp64/appendix]]
+the appearance and effect of a Horizontal Vector Reduction. Due
+to the unusual decoupling it is also possible to perform
+prefix-sum in certain circumstances. Details are in the [[svp64/appendix]]

 
 # Fail-on-first
 
 
 # Fail-on-first