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author
lkcl
<lkcl@web>
Sun, 4 Jun 2023 17:15:46 +0000
(18:15 +0100)
committer
IkiWiki
<ikiwiki.info>
Sun, 4 Jun 2023 17:15:46 +0000
(18:15 +0100)
openpower/sv/rfc/ls010/trial_addi.mdwn
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diff --git
a/openpower/sv/rfc/ls010/trial_addi.mdwn
b/openpower/sv/rfc/ls010/trial_addi.mdwn
index e76a79945a2dda937bf1dbc85eb4992e7a4976e9..a71413ba4cc4f4357a7ee684be9d51c8264157dd 100644
(file)
--- a/
openpower/sv/rfc/ls010/trial_addi.mdwn
+++ b/
openpower/sv/rfc/ls010/trial_addi.mdwn
@@
-8,13
+8,15
@@
The idea here is to review a modified version of a Power ISA 3
instruction definition, to add SVP64 in a completely non-disruptive
fashion.
instruction definition, to add SVP64 in a completely non-disruptive
fashion.
+The proposal is therefore to add a clear alternative "Operand namespace",
+which already has precedent from EXT1xx-Prefixed instructions.
# SVP64-annotated addi instruction (prototype)
**Add Immediate** D-Form
# SVP64-annotated addi instruction (prototype)
**Add Immediate** D-Form
-*
addi RT,RA,SI
+*
`addi RT,RA,SI`
```
Defined Word-instruction:
```
Defined Word-instruction:
@@
-22,13
+24,13
@@
fashion.
| 0 | 6 | 11 | 16 31 |
```
| 0 | 6 | 11 | 16 31 |
```
-*
Operand RTL
.RA <- `D-Form.RA`
-*
Operand RTL
.RT <- `D-Form.RT`
-*
Operand RTL
.SI <- `D-Form.SI`
+*
pseudocode
.RA <- `D-Form.RA`
+*
pseudocode
.RT <- `D-Form.RT`
+*
pseudocode
.SI <- `D-Form.SI`
**Prefixed Add Immediate** MLS:D-form
**Prefixed Add Immediate** MLS:D-form
-*
paddi RT,RA,SI,R
+*
`paddi RT,RA,SI,R`
```
Prefix:
```
Prefix:
@@
-39,14
+41,15
@@
fashion.
| 14 | RT | RA | si1 |
| 0 | 6 | 11 | 16 31 |
```
| 14 | RT | RA | si1 |
| 0 | 6 | 11 | 16 31 |
```
+Operands:
-*
Operand RTL
.RA <- `D-Form.RA`
-*
Operand RTL
.RT <- `D-Form.RT`
-*
Operand RTL
.SI <- `MLS.si0 || MLS.si1`
+*
pseudocode
.RA <- `D-Form.RA`
+*
pseudocode
.RT <- `D-Form.RT`
+*
pseudocode
.SI <- `MLS.si0 || MLS.si1`
**Vectorized Add Immediate** SVP64-RM-1S1D/EXTRA3/Normal:D-form
**Vectorized Add Immediate** SVP64-RM-1S1D/EXTRA3/Normal:D-form
-*
sv.addi RT,RA,SI (Vectorised on *RT and *RA)
+*
`sv.addi RT,RA,SI`
```
Prefix:
```
Prefix:
@@
-57,9
+60,11
@@
fashion.
| 0 | 6 | 11 | 16 31 |
```
| 0 | 6 | 11 | 16 31 |
```
-* Operand RTL.RA <- `SVP64_EXTRA3_DECODE(D-Form.RA, SVP64.RM.EXTRA[0:2])`
-* Operand RTL.RT <- `SVP64_EXTRA3_DECODE(D-Form.RA, SVP64.RM.EXTRA[3:5])`
-* Operand RTL.SI <- `D-Form.SI`
+Operands:
+
+* pseudocode.RA <- `SVP64_EXTRA3_DECODE(D-Form.RA, SVP64.RM.EXTRA[0:2])`
+* pseudocode.RT <- `SVP64_EXTRA3_DECODE(D-Form.RT, SVP64.RM.EXTRA[3:5])`
+* pseudocode.SI <- `D-Form.SI`
Pseudo-code:
Pseudo-code:
@@
-75,5
+80,7
@@
Pseudo-code:
Special Registers Altered:
Special Registers Altered:
+```
None
None
+```