+## Link to Function Units
+
+The Decoder (PowerDecode2) knows which registers are needed, however what
+it does not know is:
+
+* which Register file ports to connect to (this is defined by regspecs)
+* the order of those regfile ports (again: defined by regspecs)
+
+Neither do the Phase-aware Function Units (derived from MultiCompUnit)
+themselves know anything about the PowerDecoder, and they certainly
+do not know when a given instruction will need to tell *them* to read
+RA, or RB. For example: negation of RA only requires one operand,
+where add RA, RB requires two. Who tells whom that information, when
+the ALU's job is simply to add, and the Decoder's job is simply to decode?
+
+This is where a special function called "rdflags()" comes into play.
+rdflags works closely in conjunction with regspecs and the PowerDecoder2,
+in each Function Unit's "pipe\_data.py" file. It defines the flags that
+determine, from current instruction, whether the Function Unit actually
+*wants* any given Register Read Ports activated or not.
+
+That dynamically-determined information will then actively disable
+(or allow) Register file Read requests (rd.req) on a per-port basis.
+
+* [[architecture/regfiles]]
+* [CompUnits](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/compunits/compunits.py;hb=HEAD)
+* [ALU pipe_data.py specification](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/alu/pipe_data.py;hb=HEAD)
+