+static inline void
+gen6_emit_MI_STORE_DATA_IMM(const struct ilo_dev_info *dev,
+ struct intel_bo *bo, uint32_t bo_offset,
+ uint64_t val, bool store_qword,
+ struct ilo_cp *cp)
+{
+ const uint32_t cmd = ILO_GPE_MI(0x20);
+ const uint8_t cmd_len = (store_qword) ? 5 : 4;
+ /* must use GGTT on GEN6 as in PIPE_CONTROL */
+ const uint32_t cmd_flags = (dev->gen == ILO_GEN(6)) ? (1 << 22) : 0;
+ const uint32_t read_domains = INTEL_DOMAIN_INSTRUCTION;
+ const uint32_t write_domain = INTEL_DOMAIN_INSTRUCTION;
+
+ ILO_GPE_VALID_GEN(dev, 6, 7.5);
+
+ assert(bo_offset % ((store_qword) ? 8 : 4) == 0);
+
+ ilo_cp_begin(cp, cmd_len);
+ ilo_cp_write(cp, cmd | cmd_flags | (cmd_len - 2));
+ ilo_cp_write(cp, 0);
+ ilo_cp_write_bo(cp, bo_offset, bo, read_domains, write_domain);
+ ilo_cp_write(cp, (uint32_t) val);
+
+ if (store_qword)
+ ilo_cp_write(cp, (uint32_t) (val >> 32));
+ else
+ assert(val == (uint64_t) ((uint32_t) val));
+
+ ilo_cp_end(cp);
+}
+
+static inline void
+gen6_emit_MI_LOAD_REGISTER_IMM(const struct ilo_dev_info *dev,
+ uint32_t reg, uint32_t val,
+ struct ilo_cp *cp)
+{
+ const uint32_t cmd = ILO_GPE_MI(0x22);
+ const uint8_t cmd_len = 3;
+
+ ILO_GPE_VALID_GEN(dev, 6, 7.5);
+
+ assert(reg % 4 == 0);
+
+ ilo_cp_begin(cp, cmd_len);
+ ilo_cp_write(cp, cmd | (cmd_len - 2));
+ ilo_cp_write(cp, reg);
+ ilo_cp_write(cp, val);
+ ilo_cp_end(cp);
+}
+
+static inline void
+gen6_emit_MI_STORE_REGISTER_MEM(const struct ilo_dev_info *dev,
+ struct intel_bo *bo, uint32_t bo_offset,
+ uint32_t reg, struct ilo_cp *cp)
+{
+ const uint32_t cmd = ILO_GPE_MI(0x24);
+ const uint8_t cmd_len = 3;
+ /* must use GGTT on GEN6 as in PIPE_CONTROL */
+ const uint32_t cmd_flags = (dev->gen == ILO_GEN(6)) ? (1 << 22) : 0;
+ const uint32_t read_domains = INTEL_DOMAIN_INSTRUCTION;
+ const uint32_t write_domain = INTEL_DOMAIN_INSTRUCTION;
+
+ ILO_GPE_VALID_GEN(dev, 6, 7.5);
+
+ assert(reg % 4 == 0 && bo_offset % 4 == 0);
+
+ ilo_cp_begin(cp, cmd_len);
+ ilo_cp_write(cp, cmd | cmd_flags | (cmd_len - 2));
+ ilo_cp_write(cp, reg);
+ ilo_cp_write_bo(cp, bo_offset, bo, read_domains, write_domain);
+ ilo_cp_end(cp);
+}
+
+static inline void
+gen6_emit_MI_REPORT_PERF_COUNT(const struct ilo_dev_info *dev,
+ struct intel_bo *bo, uint32_t bo_offset,
+ uint32_t report_id, struct ilo_cp *cp)
+{
+ const uint32_t cmd = ILO_GPE_MI(0x28);
+ const uint8_t cmd_len = 3;
+ const uint32_t read_domains = INTEL_DOMAIN_INSTRUCTION;
+ const uint32_t write_domain = INTEL_DOMAIN_INSTRUCTION;
+
+ ILO_GPE_VALID_GEN(dev, 6, 7.5);
+
+ assert(bo_offset % 64 == 0);
+
+ /* must use GGTT on GEN6 as in PIPE_CONTROL */
+ if (dev->gen == ILO_GEN(6))
+ bo_offset |= 0x1;
+
+ ilo_cp_begin(cp, cmd_len);
+ ilo_cp_write(cp, cmd | (cmd_len - 2));
+ ilo_cp_write_bo(cp, bo_offset, bo, read_domains, write_domain);
+ ilo_cp_write(cp, report_id);
+ ilo_cp_end(cp);
+}
+