+ rtx_insn *next_active = next_active_insn (insn);
+ /* Undo delay slots to avoid bubbles if the next instruction can
+ be placed in a forbidden slot or the cost of adding an
+ explicit NOP in a forbidden slot is OK and if the SEQUENCE is
+ safely breakable. */
+ if (TARGET_CB_MAYBE
+ && mips_breakable_sequence_p (insn)
+ && INSN_P (SEQ_BEGIN (insn))
+ && INSN_P (SEQ_END (insn))
+ && ((next_active
+ && INSN_P (next_active)
+ && GET_CODE (PATTERN (next_active)) != SEQUENCE
+ && get_attr_can_delay (next_active) == CAN_DELAY_YES)
+ || !optimize_size))
+ {
+ /* To hide a potential pipeline bubble, if we scan backwards
+ from the current SEQUENCE and find that there is a load
+ of a value that is used in the CTI and there are no
+ dependencies between the CTI and instruction in the delay
+ slot, break the sequence so the load delay is hidden. */
+ HARD_REG_SET uses;
+ CLEAR_HARD_REG_SET (uses);
+ note_uses (&PATTERN (SEQ_BEGIN (insn)), record_hard_reg_uses,
+ &uses);
+ HARD_REG_SET delay_sets;
+ CLEAR_HARD_REG_SET (delay_sets);
+ note_stores (PATTERN (SEQ_END (insn)), record_hard_reg_sets,
+ &delay_sets);
+
+ rtx_insn *prev = prev_active_insn (insn);
+ if (prev
+ && GET_CODE (PATTERN (prev)) == SET
+ && MEM_P (SET_SRC (PATTERN (prev))))
+ {
+ HARD_REG_SET sets;
+ CLEAR_HARD_REG_SET (sets);
+ note_stores (PATTERN (prev), record_hard_reg_sets,
+ &sets);
+
+ /* Re-order if safe. */
+ if (!hard_reg_set_intersect_p (delay_sets, uses)
+ && hard_reg_set_intersect_p (uses, sets))
+ {
+ next_insn = mips_break_sequence (insn);
+ /* Need to process the hazards of the newly
+ introduced instructions. */
+ continue;
+ }
+ }
+
+ /* If we find an orphaned high-part relocation in a delay
+ slot then we can convert to a compact branch and get
+ the orphaned high part deleted. */
+ if (mips_orphaned_high_part_p (&htab, SEQ_END (insn)))
+ {
+ next_insn = mips_break_sequence (insn);
+ /* Need to process the hazards of the newly
+ introduced instructions. */
+ continue;
+ }
+ }
+