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mention AMD RDNA
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Wed, 11 Sep 2019 11:42:01 +0000
(12:42 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Wed, 11 Sep 2019 11:42:01 +0000
(12:42 +0100)
ztrans_proposal.mdwn
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diff --git
a/ztrans_proposal.mdwn
b/ztrans_proposal.mdwn
index 8a0fdf909884efee3e9cf9ccf5b75ea956993432..7a6b03803e08542947fb6d9c37bd333a1b334793 100644
(file)
--- a/
ztrans_proposal.mdwn
+++ b/
ztrans_proposal.mdwn
@@
-462,7
+462,8
@@
Vivante Embedded/Mobile 3D (etnaviv <https://github.com/laanwj/etna_viv/blob/mas
It also has fast variants of some of these, as a CSR Mode.
It also has fast variants of some of these, as a CSR Mode.
-AMD's R600 GPU (R600\_Instruction\_Set\_Architecture.pdf) has:
+AMD's R600 GPU (R600\_Instruction\_Set\_Architecture.pdf) and the
+RDNA ISA (RDNA\_Shader\_ISA\_5August2019.pdf, Table 22, Section 6.3) have:
COS (appx)
EXP2
COS (appx)
EXP2
@@
-472,6
+473,11
@@
AMD's R600 GPU (R600\_Instruction\_Set\_Architecture.pdf) has:
SQRT
SIN (appx)
SQRT
SIN (appx)
+AMD RDNA has F16 and F32 variants of all the above, and also has F64
+variants of SQRT, RSQRT and RECIP. It is interesting that even the
+modern high-end AMD GPU does not have TAN or ATAN, where MALI Midgard
+does.
+
Also a general point, that customised optimised hardware targetting
FP32 3D with less accuracy simply can neither be used for IEEE754 nor
for FP64 (except as a starting point for hardware or software driven
Also a general point, that customised optimised hardware targetting
FP32 3D with less accuracy simply can neither be used for IEEE754 nor
for FP64 (except as a starting point for hardware or software driven