When zero extending a 32-bit register, we emit a "mov", but currently
report the cost of the "mov" incorrectly.
In terms of speed, we currently say the cost is that of an extend
operation. But the cost of a "mov" is the cost of 1 instruction, so fix
that.
In terms of size, we currently say that the "mov" takes 0 instructions.
Fix it by changing it to 1.
Bootstrapped and tested on aarch64-none-elf.
gcc/
* config/aarch64/aarch64.c (aarch64_rtx_costs): Fix cost of zero extend.
From-SVN: r238820
+2016-07-28 Kristina Martsenko <kristina.martsenko@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_rtx_costs): Fix cost of zero extend.
+
2016-07-28 Wilco Dijkstra <wdijkstr@arm.com>
* config/aarch64/aarch64.c (aarch64_pushwb_pair_reg): Rename.
2016-07-28 Wilco Dijkstra <wdijkstr@arm.com>
* config/aarch64/aarch64.c (aarch64_pushwb_pair_reg): Rename.
{
int op_cost = rtx_cost (op0, VOIDmode, ZERO_EXTEND, 0, speed);
{
int op_cost = rtx_cost (op0, VOIDmode, ZERO_EXTEND, 0, speed);
- if (!op_cost && speed)
- /* MOV. */
- *cost += extra_cost->alu.extend;
- else
- /* Free, the cost is that of the SI mode operation. */
+ /* If OP_COST is non-zero, then the cost of the zero extend
+ is effectively the cost of the inner operation. Otherwise
+ we have a MOV instruction and we take the cost from the MOV
+ itself. This is true independently of whether we are
+ optimizing for space or time. */
+ if (op_cost)
*cost = op_cost;
return true;
*cost = op_cost;
return true;