The v3d_qpu_writes_r*() were only checking for fixed-function accumulator
writes, not normal ALU writes to those regs.
Fixes fs-discard-exit-2 on simulation (but not HW).
case V3D_QPU_WADDR_R0:
case V3D_QPU_WADDR_R1:
case V3D_QPU_WADDR_R2:
case V3D_QPU_WADDR_R0:
case V3D_QPU_WADDR_R1:
case V3D_QPU_WADDR_R2:
- case V3D_QPU_WADDR_R3:
- case V3D_QPU_WADDR_R4:
- case V3D_QPU_WADDR_R5:
add_write_dep(state,
&state->last_r[waddr - V3D_QPU_WADDR_R0],
n);
break;
add_write_dep(state,
&state->last_r[waddr - V3D_QPU_WADDR_R0],
n);
break;
+ case V3D_QPU_WADDR_R3:
+ case V3D_QPU_WADDR_R4:
+ case V3D_QPU_WADDR_R5:
+ /* Handled by v3d_qpu_writes_r*() checks below. */
+ break;
case V3D_QPU_WADDR_VPM:
case V3D_QPU_WADDR_VPMU:
case V3D_QPU_WADDR_VPM:
case V3D_QPU_WADDR_VPMU:
bool
v3d_qpu_writes_r3(const struct v3d_qpu_instr *inst)
{
bool
v3d_qpu_writes_r3(const struct v3d_qpu_instr *inst)
{
+ if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
+ if (inst->alu.add.magic_write &&
+ inst->alu.add.waddr == V3D_QPU_WADDR_R3) {
+ return true;
+ }
+
+ if (inst->alu.mul.magic_write &&
+ inst->alu.mul.waddr == V3D_QPU_WADDR_R3) {
+ return true;
+ }
+ }
+
return inst->sig.ldvary || inst->sig.ldvpm;
}
return inst->sig.ldvary || inst->sig.ldvpm;
}
if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
if (inst->alu.add.magic_write &&
if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
if (inst->alu.add.magic_write &&
- v3d_qpu_magic_waddr_is_sfu(inst->alu.add.waddr)) {
+ (inst->alu.add.waddr == V3D_QPU_WADDR_R4 ||
+ v3d_qpu_magic_waddr_is_sfu(inst->alu.add.waddr))) {
return true;
}
if (inst->alu.mul.magic_write &&
return true;
}
if (inst->alu.mul.magic_write &&
- v3d_qpu_magic_waddr_is_sfu(inst->alu.mul.waddr)) {
+ (inst->alu.mul.waddr == V3D_QPU_WADDR_R4 ||
+ v3d_qpu_magic_waddr_is_sfu(inst->alu.mul.waddr))) {
bool
v3d_qpu_writes_r5(const struct v3d_qpu_instr *inst)
{
bool
v3d_qpu_writes_r5(const struct v3d_qpu_instr *inst)
{
+ if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
+ if (inst->alu.add.magic_write &&
+ inst->alu.add.waddr == V3D_QPU_WADDR_R5) {
+ return true;
+ }
+
+ if (inst->alu.mul.magic_write &&
+ inst->alu.mul.waddr == V3D_QPU_WADDR_R5) {
+ return true;
+ }
+ }
+
return inst->sig.ldvary || inst->sig.ldunif;
}
return inst->sig.ldvary || inst->sig.ldunif;
}