adapt migScope to Migen changes

diff --git a/examples/de0_nano/constraints.py b/examples/de0_nano/constraints.py
index b780de216f7859f975fef9cd12e2cca2cc2b9e32..766734de5baeb845326c0a2515fdd188fb8b3887 100644 (file)
--- a/examples/de0_nano/constraints.py
+++ b/examples/de0_nano/constraints.py
@@ -4,7 +4,7 @@ class Constraints:
                def add(signal, pin, vec=-1, iostandard="3.3-V LVTTL", extra="", sch=""):
                        self.constraints.append((signal, vec, pin, iostandard, extra,sch))
                def add_vec(signal, pins, iostandard="3.3-V LVTTL", extra="", sch=""):
                def add(signal, pin, vec=-1, iostandard="3.3-V LVTTL", extra="", sch=""):
                        self.constraints.append((signal, vec, pin, iostandard, extra,sch))
                def add_vec(signal, pins, iostandard="3.3-V LVTTL", extra="", sch=""):

-                       assert(signal.bv.width == len(pins)), "%s size : %d / qsf size : %d" %(signal,signal.bv.width,len(pins))
+                       assert(signal.nbits == len(pins)), "%s size : %d / qsf size : %d" %(signal,signal.bv.width,len(pins))

                        i = 0
                        for p in pins:
                                add(signal, p, i, iostandard, extra)
                        i = 0
                        for p in pins:
                                add(signal, p, i, iostandard, extra)

diff --git a/examples/de0_nano/top.py b/examples/de0_nano/top.py
index 362de76fdad474025ef7843ca889777a1adb1535..92454650e1e4fe91a7aa716d6fca773c86d25e86 100644 (file)
--- a/examples/de0_nano/top.py
+++ b/examples/de0_nano/top.py
@@ -102,11 +102,11 @@ def get():
        # Csr Interconnect
        csrcon0 = csr.Interconnect(spi2csr0.csr, 
                        [
        # Csr Interconnect
        csrcon0 = csr.Interconnect(spi2csr0.csr, 
                        [

-                               migIo0.bank.interface,
-                               migLa0.trig.bank.interface,
-                               migLa0.rec.bank.interface,
-                               migLa1.trig.bank.interface,
-                               migLa1.rec.bank.interface,
+                               migIo0.bank.bus,
+                               migLa0.trig.bank.bus,
+                               migLa0.rec.bank.bus,
+                               migLa1.trig.bank.bus,
+                               migLa1.rec.bank.bus,

                                
                        ])
        comb = []
                                
                        ])
        comb = []


@@ -117,13 +117,13 @@ def get():
        #
        
        # Counter
        #
        
        # Counter

-       cnt_gen = Signal(BV(8))
+       cnt_gen = Signal(8)

        sync += [
                cnt_gen.eq(cnt_gen+1)
        ]
        
        # Square
        sync += [
                cnt_gen.eq(cnt_gen+1)
        ]
        
        # Square

-       square_gen = Signal(BV(8))
+       square_gen = Signal(8)

        sync += [
                If(cnt_gen[7],
                        square_gen.eq(255)
        sync += [
                If(cnt_gen[7],
                        square_gen.eq(255)


@@ -134,13 +134,18 @@ def get():
        
        sinus = [int(128*sin((2*3.1415)/256*(x+1)))+128 for x in range(256)]
        sinus_re = Signal()
        
        sinus = [int(128*sin((2*3.1415)/256*(x+1)))+128 for x in range(256)]
        sinus_re = Signal()

-       sinus_gen = Signal(BV(8))
+       sinus_gen = Signal(8)

        comb +=[sinus_re.eq(1)]
        comb +=[sinus_re.eq(1)]

-       sinus_port = MemoryPort(adr=cnt_gen, re=sinus_re, dat_r=sinus_gen)
-       sinus_mem = Memory(8, 256, sinus_port, init = sinus)
+       sinus_mem = Memory(8, 256, init = sinus)
+       sinus_port = sinus_mem.get_port(has_re=True)
+       comb += [
+               sinus_port.adr.eq(cnt_gen),
+               sinus_port.re.eq(sinus_re),
+               sinus_gen.eq(sinus_port.dat_r)
+       ]

        
        # Signal Selection
        
        # Signal Selection

-       sig_gen = Signal(BV(8))
+       sig_gen = Signal(8)

        comb += [
                If(migIo0.o == 0,
                        sig_gen.eq(cnt_gen)
        comb += [
                If(migIo0.o == 0,
                        sig_gen.eq(cnt_gen)


@@ -154,7 +159,7 @@ def get():
        ]
        
        # Led
        ]
        
        # Led

-       led0 = Signal(BV(8))
+       led0 = Signal(8)

        comb += [led0.eq(migIo0.o[:8])]
        
        
        comb += [led0.eq(migIo0.o[:8])]
        
        


@@ -187,7 +192,7 @@ def get():
        cst = Constraints(in_rst_n, cd_in, spi2csr0, led0)
        src_verilog, vns = verilog.convert(frag,
                cst.get_ios(),
        cst = Constraints(in_rst_n, cd_in, spi2csr0, led0)
        src_verilog, vns = verilog.convert(frag,
                cst.get_ios(),

-               name="de1",
+               name="de0_nano",

                clock_domains={
                        "sys": cd_in
                },
                clock_domains={
                        "sys": cd_in
                },

diff --git a/examples/de1/constraints.py b/examples/de1/constraints.py
index 421fdd4d80da8f03eb70a34ff483892d5031d6e2..b5bb3ce66db995d8ac1604927ea73a907f09cf0d 100644 (file)
--- a/examples/de1/constraints.py
+++ b/examples/de1/constraints.py
@@ -4,7 +4,7 @@ class Constraints:
                def add(signal, pin, vec=-1, iostandard="3.3-V LVTTL", extra="", sch=""):
                        self.constraints.append((signal, vec, pin, iostandard, extra,sch))
                def add_vec(signal, pins, iostandard="3.3-V LVTTL", extra="", sch=""):
                def add(signal, pin, vec=-1, iostandard="3.3-V LVTTL", extra="", sch=""):
                        self.constraints.append((signal, vec, pin, iostandard, extra,sch))
                def add_vec(signal, pins, iostandard="3.3-V LVTTL", extra="", sch=""):

-                       assert(signal.bv.width == len(pins)), "%s size : %d / qsf size : %d" %(signal,signal.bv.width,len(pins))
+                       assert(signal.nbits == len(pins)), "%s size : %d / qsf size : %d" %(signal,signal.bv.width,len(pins))

                        i = 0
                        for p in pins:
                                add(signal, p, i, iostandard, extra)
                        i = 0
                        for p in pins:
                                add(signal, p, i, iostandard, extra)

diff --git a/examples/de1/top.py b/examples/de1/top.py
index c4558d53a336df512173beb4b54ff46fe3dce0df..b8711a2ba422d437f99ef22f2086c8ff43de0977 100644 (file)
--- a/examples/de1/top.py
+++ b/examples/de1/top.py
@@ -102,11 +102,11 @@ def get():
        # Csr Interconnect
        csrcon0 = csr.Interconnect(spi2csr0.csr, 
                        [
        # Csr Interconnect
        csrcon0 = csr.Interconnect(spi2csr0.csr, 
                        [

-                               migIo0.bank.interface,
-                               migLa0.trig.bank.interface,
-                               migLa0.rec.bank.interface,
-                               migLa1.trig.bank.interface,
-                               migLa1.rec.bank.interface,
+                               migIo0.bank.bus,
+                               migLa0.trig.bank.bus,
+                               migLa0.rec.bank.bus,
+                               migLa1.trig.bank.bus,
+                               migLa1.rec.bank.bus,

                                
                        ])
        comb = []
                                
                        ])
        comb = []


@@ -117,13 +117,13 @@ def get():
        #
        
        # Counter
        #
        
        # Counter

-       cnt_gen = Signal(BV(8))
+       cnt_gen = Signal(8)

        sync += [
                cnt_gen.eq(cnt_gen+1)
        ]
        
        # Square
        sync += [
                cnt_gen.eq(cnt_gen+1)
        ]
        
        # Square

-       square_gen = Signal(BV(8))
+       square_gen = Signal(8)

        sync += [
                If(cnt_gen[7],
                        square_gen.eq(255)
        sync += [
                If(cnt_gen[7],
                        square_gen.eq(255)


@@ -134,13 +134,18 @@ def get():
        
        sinus = [int(128*sin((2*3.1415)/256*(x+1)))+128 for x in range(256)]
        sinus_re = Signal()
        
        sinus = [int(128*sin((2*3.1415)/256*(x+1)))+128 for x in range(256)]
        sinus_re = Signal()

-       sinus_gen = Signal(BV(8))
+       sinus_gen = Signal(8)

        comb +=[sinus_re.eq(1)]
        comb +=[sinus_re.eq(1)]

-       sinus_port = MemoryPort(adr=cnt_gen, re=sinus_re, dat_r=sinus_gen)
-       sinus_mem = Memory(8, 256, sinus_port, init = sinus)
+       sinus_mem = Memory(8, 256, init = sinus)
+       sinus_port = sinus_mem.get_port(has_re=True)
+       comb += [
+               sinus_port.adr.eq(cnt_gen),
+               sinus_port.re.eq(sinus_re),
+               sinus_gen.eq(sinus_port.dat_r)
+       ]

        
        # Signal Selection
        
        # Signal Selection

-       sig_gen = Signal(BV(8))
+       sig_gen = Signal(8)

        comb += [
                If(migIo0.o == 0,
                        sig_gen.eq(cnt_gen)
        comb += [
                If(migIo0.o == 0,
                        sig_gen.eq(cnt_gen)


@@ -154,11 +159,11 @@ def get():
        ]
        
        # Led
        ]
        
        # Led

-       led0 = Signal(BV(8))
+       led0 = Signal(8)

        comb += [led0.eq(migIo0.o[:8])]
        
        #Switch
        comb += [led0.eq(migIo0.o[:8])]
        
        #Switch

-       sw0 = Signal(BV(8))
+       sw0 = Signal(8)

        comb += [migIo0.i.eq(sw0)]
        
        # MigLa0 input
        comb += [migIo0.i.eq(sw0)]
        
        # MigLa0 input

diff --git a/migScope/migIo.py b/migScope/migIo.py
index fba310adb2d19f9a17a9713675f0589525ed8c8c..5e4ff4fac3bd001f32c3d905d3e309b874aa8a78 100644 (file)
--- a/migScope/migIo.py
+++ b/migScope/migIo.py
@@ -15,11 +15,11 @@ class MigIo:
                self.interface = interface
                self.words = int(2**bits_for(width-1)/8)
                if "I" in self.mode:
                self.interface = interface
                self.words = int(2**bits_for(width-1)/8)
                if "I" in self.mode:

-                       self.i = Signal(BV(self.width))
+                       self.i = Signal(self.width)

                        self.ireg = description.RegisterField("i", self.width, READ_ONLY, WRITE_ONLY)
                        self.ireg.field.w.name_override = "inputs"
                if "O" in self.mode:
                        self.ireg = description.RegisterField("i", self.width, READ_ONLY, WRITE_ONLY)
                        self.ireg.field.w.name_override = "inputs"
                if "O" in self.mode:

-                       self.o = Signal(BV(self.width))
+                       self.o = Signal(self.width)

                        self.oreg = description.RegisterField("o", self.width)
                        self.oreg.field.r.name_override = "ouptuts"
                self.bank = csrgen.Bank([self.oreg, self.ireg], address=self.address)
                        self.oreg = description.RegisterField("o", self.width)
                        self.oreg.field.r.name_override = "ouptuts"
                self.bank = csrgen.Bank([self.oreg, self.ireg], address=self.address)

diff --git a/migScope/migLa.py b/migScope/migLa.py
index 93f305aa549e88665e03d898be4e5caadaee2846..781ccb35a72c4b3b67a7096e14426e5b0eea3f7f 100644 (file)
--- a/migScope/migLa.py
+++ b/migScope/migLa.py
@@ -15,8 +15,8 @@ class MigLa:
                self.rec = rec
                self.interface = interface
                
                self.rec = rec
                self.interface = interface
                

-               self.in_trig = Signal(BV(self.trig.trig_width))
-               self.in_dat  = Signal(BV(self.trig.trig_width))
+               self.in_trig = Signal(self.trig.trig_width)
+               self.in_dat  = Signal(self.trig.trig_width)

                
                self.trig.set_address(self.address)
                self.rec.set_address(self.address + 0x0200)
                
                self.trig.set_address(self.address)
                self.rec.set_address(self.address + 0x0200)

diff --git a/migScope/recorder.py b/migScope/recorder.py
index 0c2aec1a5a19523e2873f92182b2e4d4d6578717..ebfc9d43000835a62f53bc964ba17e5225a6fbc1 100644 (file)
--- a/migScope/recorder.py
+++ b/migScope/recorder.py
@@ -15,30 +15,43 @@ class Storage:
                #Control
                self.rst = Signal()
                self.start = Signal()
                #Control
                self.rst = Signal()
                self.start = Signal()

-               self.offset = Signal(BV(self.depth_width))
-               self.size = Signal(BV(self.depth_width))
+               self.offset = Signal(self.depth_width)
+               self.size = Signal(self.depth_width)

                self.done = Signal()
                self.run = Signal()
                self.done = Signal()
                self.run = Signal()

+               
+               #Others
+               self._mem = Memory(self.width, self.depth)
+               

                #Write Path
                self.put = Signal()
                #Write Path
                self.put = Signal()

-               self.put_dat = Signal(BV(self.width))
-               self._put_ptr = Signal(BV(self.depth_width))
-               self._put_ptr_stop = Signal(BV(self.depth_width))
-               self._put_port = MemoryPort(adr=self._put_ptr, we=self.put, dat_w=self.put_dat)
+               self.put_dat = Signal(self.width)
+               self._put_ptr = Signal(self.depth_width)
+               self._put_ptr_stop = Signal(self.depth_width)
+               self._put_port = self._mem.get_port(write_capable=True)
+               

                #Read Path
                self.get = Signal()
                #Read Path
                self.get = Signal()

-               self.get_dat = Signal(BV(self.width))
-               self._get_ptr = Signal(BV(self.depth_width))
-               self._get_port = MemoryPort(adr=self._get_ptr, re=self.get, dat_r=self.get_dat)
-               #Others
-               self._mem = Memory(self.width, self.depth, self._put_port, self._get_port)
+               self.get_dat = Signal(self.width)
+               self._get_ptr = Signal(self.depth_width)
+               self._get_port = self._mem.get_port(has_re=True)

                
                
        def get_fragment(self):
                comb = []
                sync = []
                memories = [self._mem]
                
                
        def get_fragment(self):
                comb = []
                sync = []
                memories = [self._mem]

-               size_minus_offset = Signal(BV(self.depth_width))
+               comb += [
+                               self._get_port.adr.eq(self._get_ptr),
+                               self._get_port.re.eq(self.get),
+                               self.get_dat.eq(self._get_port.dat_r),
+                               
+                               self._put_port.adr.eq(self._put_ptr),
+                               self._put_port.we.eq(self.put),
+                               self._put_port.dat_w.eq(self.put_dat)
+               ]
+               
+               size_minus_offset = Signal(self.depth_width)

                comb += [size_minus_offset.eq(self.size-self.offset)]
                
                #Control
                comb += [size_minus_offset.eq(self.size-self.offset)]
                
                #Control


@@ -82,8 +95,8 @@ class Sequencer:
                self.depth_width = bits_for(self.depth)
                # Controller interface
                self.ctl_rst = Signal()
                self.depth_width = bits_for(self.depth)
                # Controller interface
                self.ctl_rst = Signal()

-               self.ctl_offset = Signal(BV(self.depth_width))
-               self.ctl_size = Signal(BV(self.depth_width))
+               self.ctl_offset = Signal(self.depth_width)
+               self.ctl_size = Signal(self.depth_width)

                self.ctl_arm = Signal()
                self.ctl_done = Signal()
                self._ctl_arm_d = Signal()
                self.ctl_arm = Signal()
                self.ctl_done = Signal()
                self._ctl_arm_d = Signal()


@@ -91,8 +104,8 @@ class Sequencer:
                self.trig_hit  = Signal()
                self._trig_hit_d = Signal()
                # Recorder interface
                self.trig_hit  = Signal()
                self._trig_hit_d = Signal()
                # Recorder interface

-               self.rec_offset = Signal(BV(self.depth_width))
-               self.rec_size = Signal(BV(self.depth_width))
+               self.rec_offset = Signal(self.depth_width)
+               self.rec_size = Signal(self.depth_width)

                self.rec_start = Signal()
                self.rec_done  = Signal()
                # Others
                self.rec_start = Signal()
                self.rec_done  = Signal()
                # Others


@@ -154,7 +167,7 @@ class Recorder:
                
                # Trigger Interface
                self.trig_hit = Signal()
                
                # Trigger Interface
                self.trig_hit = Signal()

-               self.trig_dat = Signal(BV(self.width))
+               self.trig_dat = Signal(self.width)

        
        def set_address(self, address):
                self.address = address
        
        def set_address(self, address):
                self.address = address

diff --git a/migScope/trigger.py b/migScope/trigger.py
index 144d5747b1db9d938a9edf9eb17ba5eb7e2abe27..cde9890dcfbd088f2a6831f658a9dc742090f324 100644 (file)
--- a/migScope/trigger.py
+++ b/migScope/trigger.py
@@ -18,9 +18,9 @@ class Term:
                self.reg_size = 2*width
                self.words = int(2**bits_for(width-1)/8)
                
                self.reg_size = 2*width
                self.words = int(2**bits_for(width-1)/8)
                

-               self.i = Signal(BV(self.width))
-               self.t = Signal(BV(self.width))
-               self.m = Signal(BV(self.width))
+               self.i = Signal(self.width)
+               self.t = Signal(self.width)
+               self.m = Signal(self.width)

                self.o = Signal()
                
        def get_fragment(self):
                self.o = Signal()
                
        def get_fragment(self):


@@ -60,9 +60,9 @@ class RangeDetector:
                self.reg_size = 2*width
                self.words = int(2**bits_for(width-1)/8)
                
                self.reg_size = 2*width
                self.words = int(2**bits_for(width-1)/8)
                

-               self.i = Signal(BV(self.width))
-               self.low = Signal(BV(self.width))
-               self.high = Signal(BV(self.width))
+               self.i = Signal(self.width)
+               self.low = Signal(self.width)
+               self.high = Signal(self.width)

                self.o = Signal()
                
        def get_fragment(self):
                self.o = Signal()
                
        def get_fragment(self):


@@ -102,16 +102,16 @@ class EdgeDetector:
                self.reg_base = 0
                self.reg_size = len(self.mode)*width
                
                self.reg_base = 0
                self.reg_size = len(self.mode)*width
                

-               self.i = Signal(BV(self.width))
-               self.i_d = Signal(BV(self.width))
+               self.i = Signal(self.width)
+               self.i_d = Signal(self.width)

                if "R" in self.mode:
                if "R" in self.mode:

-                       self.r_mask = Signal(BV(self.width))
+                       self.r_mask = Signal(self.width)

                        self.ro = Signal()
                if "F" in self.mode:
                        self.ro = Signal()
                if "F" in self.mode:

-                       self.f_mask = Signal(BV(self.width))
+                       self.f_mask = Signal(self.width)

                        self.fo = Signal()
                if "B" in self.mode:
                        self.fo = Signal()
                if "B" in self.mode:

-                       self.b_mask = Signal(BV(self.width))
+                       self.b_mask = Signal(self.width)

                        self.bo = Signal()
                self.o = Signal()
                
                        self.bo = Signal()
                self.o = Signal()
                


@@ -206,8 +206,8 @@ class Timer:
                self.clear = Signal()
                
                self.enable = Signal()
                self.clear = Signal()
                
                self.enable = Signal()

-               self.cnt = Signal(BV(self.width))
-               self.cnt_max = Signal(BV(self.width))
+               self.cnt = Signal(self.width)
+               self.cnt_max = Signal(self.width)

                
                self.o = Signal()
        
                
                self.o = Signal()
        


@@ -253,26 +253,37 @@ class Sum:
                self.pipe = pipe
                self.interface = None
                
                self.pipe = pipe
                self.interface = None
                

-               self.i = Signal(BV(self.width))
+               self._mem = Memory(1, 2**self.width)
+               
+               self.i = Signal(self.width)

                self._o = Signal()
                self.o = Signal()
                self._o = Signal()
                self.o = Signal()

-               self._lut_port = MemoryPort(adr=self.i, dat_r=self._o)
+               self._lut_port = self._mem.get_port()

                
                self.reg_name = "sum_reg"
                self.reg_base = 0
                self.reg_size = 32
                
                self.prog = Signal()
                
                self.reg_name = "sum_reg"
                self.reg_base = 0
                self.reg_size = 32
                
                self.prog = Signal()

-               self.prog_adr = Signal(BV(width))
+               self.prog_adr = Signal(width)

                self.prog_dat = Signal()
                self.prog_dat = Signal()

-               self._prog_port = MemoryPort(adr=self.prog_adr, we=self.prog, dat_w=self.prog_dat)
+               self._prog_port = self._mem.get_port(write_capable=True)

                
                

-               self._mem = Memory(1, 2**self.width, self._lut_port, self._prog_port)

                
        def get_fragment(self):
                comb = []
                sync = []
                memories = [self._mem]
                
        def get_fragment(self):
                comb = []
                sync = []
                memories = [self._mem]

+               comb += [
+                               self._lut_port.adr.eq(self.i),
+                               self._o.eq(self._lut_port.dat_r),
+                               
+                               self._prog_port.adr.eq(self.prog_adr),
+                               self._prog_port.we.eq(self.prog),
+                               self._prog_port.dat_w.eq(self.prog_dat)
+               ]
+               
+               

                if self.pipe:
                        sync += [self.o.eq(self._o)]
                else:
                if self.pipe:
                        sync += [self.o.eq(self._o)]
                else:


@@ -311,7 +322,7 @@ class Trigger:
                self.interface = interface
                self.sum = Sum(len(self.ports))
                
                self.interface = interface
                self.sum = Sum(len(self.ports))
                

-               self.in_trig = Signal(BV(self.trig_width))
+               self.in_trig = Signal(self.trig_width)

                
                self.hit = Signal()
                
                
                self.hit = Signal()
                

diff --git a/sim/tb_Migscope.py b/sim/tb_Migscope.py
index 8f55bbadfaba120b4b6f15f59f09680385dd4486..b27d4c61ab01e32a663d94be34bf392d46917f12 100644 (file)
--- a/sim/tb_Migscope.py
+++ b/sim/tb_Migscope.py
@@ -125,7 +125,7 @@ def main():
                                recorder0.bank.interface
                        ])
 
                                recorder0.bank.interface
                        ])
 

-       trig_sig = Signal(BV(32))
+       trig_sig = Signal(32)

        comb = []
        comb +=[
                trigger0.in_trig.eq(trig_sig)
        comb = []
        comb +=[
                trigger0.in_trig.eq(trig_sig)

diff --git a/spi2Csr/__init__.py b/spi2Csr/__init__.py
index 16b12be179f8fe005a0804876e286c06f7660590..f327762ceb8e3790c33a64a222a7f9431e892d38 100644 (file)
--- a/spi2Csr/__init__.py
+++ b/spi2Csr/__init__.py
@@ -68,10 +68,10 @@ class Spi2Csr :
                #
                # Spi --> Csr
                #
                #
                # Spi --> Csr
                #

-               spi_cnt = Signal(BV(bits_for(self.a_width+self.max_burst*self.d_width)))
-               spi_addr = Signal(BV(self.a_width))
-               spi_w_dat = Signal(BV(self.d_width))
-               spi_r_dat = Signal(BV(self.d_width))
+               spi_cnt = Signal(bits_for(self.a_width+self.max_burst*self.d_width))
+               spi_addr = Signal(self.a_width)
+               spi_w_dat = Signal(self.d_width)
+               spi_r_dat = Signal(self.d_width)

                spi_we = Signal()
                spi_re = Signal()
                spi_we_re_done = Signal(reset = 1)
                spi_we = Signal()
                spi_re = Signal()
                spi_we_re_done = Signal(reset = 1)


@@ -126,7 +126,7 @@ class Spi2Csr :
                #
                # Csr --> Spi
                #
                #
                # Csr --> Spi
                #

-               spi_r_dat_shift = Signal(BV(self.d_width))
+               spi_r_dat_shift = Signal(self.d_width)

                sync +=[
                        If(spi_re,
                                spi_r_dat_shift.eq(spi_r_dat)
                sync +=[
                        If(spi_re,
                                spi_r_dat_shift.eq(spi_r_dat)