-[[Comparative analysis|harmonised_rvv_rvp/comparative_analysis]] of Harmonised RVP vs Andes Packed SIMD ISA proposal
-
-##### MVL, setvl instruction & VL CSR work as per RV Vector spec.
-
-##### VLD and VST are supported
-
-RVP implementations may choose to load/store to/from Integer register file (rather than from a dedicated Vector register file).
-
-* Thus, RVP implementations have a choice of providing a dedicated Vector register file, or sharing the integer register file, but not both simultaneously. (Supporting both would need a CSR mode switch bit).
-* Mapping of v0-31 <-> r0-31 **is fixed** at 1:1. (An exception may be made to map v1 to r5, as otherwise may clash with procedure linkage).
-* VLD and VST in this case will have similar behaviour to LW/LD and SW/SD respectively, but only operate on up to VL elements (see point #4 below).
-* If integer register file is used for vector operations, any callee saved registers (r2-4, 8-9, 18-27) must be saved with RVI SW or SD instructions, before being used as vector registers (this register saving behaviour is harmless but redundant when RVP code is run on a machine with a dedicated vector reg file).
-
-##### VLDX, VSTX, VLDS, VSTS are not supported in hardware
-To keep RVP implementations simple, these instructions will trap, and may be implemented as software emulation
-
-##### Default register "banks" and types
-
-In the absence of an explicit VCFG setup, the vector registers (when shared with Integer register file) are to default into two “banks” as follows:
-
-* v0-v15: vectors with INT8 elements, split into 8 x signed (v0-v7) & 8 x unsigned (v8-v15)
-* v16-v29: vectors with INT16 elements, split into 8 x signed (v16-v23) & 6 x unsigned (v24-v29)
-
-Having the above default vector type configuration harmonises most of the Andes SIMD instruction set (which explicitly encodes INT8 vs INT16 vector types as separate instructions). The main change from the Andes SIMD proposal is that instructions are restricted to 14 registers of each vector element type (with element size explicitly encoded in the most significant bit of the 5 bit register specifier fields).
+[[Comparative analysis|harmonised_rvv_rvp/comparative_analysis]] of
+Harmonised RVP vs Andes Packed SIMD ISA proposal
+
+## MVL, setvl instruction & VL CSR work as per RV Vector spec.
+
+## VLD and VST are supported
+
+RVP implementations may choose to load/store to/from Integer register file
+(rather than from a dedicated Vector register file).
+
+* Thus, RVP implementations have a choice of providing a dedicated
+ Vector register file, or sharing the integer register file, but not
+ both simultaneously. (Supporting both would need a CSR mode switch bit).
+* Mapping of v0-31 <-> r0-31 **is fixed** at 1:1. (An exception may be
+ made to map v1 to r5, as otherwise may clash with procedure linkage).
+* VLD and VST in this case will have similar behaviour to LW/LD and SW/SD
+ respectively, but only operate on up to VL elements (see point #4 below).
+* If integer register file is used for vector operations, any callee saved
+ registers (r2-4, 8-9, 18-27) must be saved with RVI SW or SD instructions,
+ before being used as vector registers (this register saving behaviour is
+ harmless but redundant when RVP code is run on a machine with a dedicated
+ vector reg file).
+
+## VLDX, VSTX, VLDS, VSTS are not supported in hardware
+To keep RVP implementations simple, these instructions will trap, and
+may be implemented as software emulation
+
+## Default register "banks" and types
+
+In the absence of an explicit VCFG setup, the vector registers (when
+shared with Integer register file) are to default into two “banks”
+as follows:
+
+* v0-v15: vectors with INT8 elements, split into 8 x signed (v0-v7)
+ & 8 x unsigned (v8-v15)
+* v16-v29: vectors with INT16 elements, split into 8 x signed (v16-v23)
+ & 6 x unsigned (v24-v29)
+
+Having the above default vector type configuration harmonises most of
+the Andes SIMD instruction set (which explicitly encodes INT8 vs INT16
+vector types as separate instructions). The main change from the Andes
+SIMD proposal is that instructions are restricted to 14 registers of
+each vector element type (with element size explicitly encoded in the
+most significant bit of the 5 bit register specifier fields).