+/* Implement DBX_REGISTER_NUMBER macro.
+
+ Return the DWARF register number that corresponds to the GCC internal
+ REGNO. */
+
+unsigned int
+gcn_dwarf_register_number (unsigned int regno)
+{
+ /* Registers defined in DWARF. */
+ if (regno == EXEC_LO_REG)
+ return 17;
+ /* We need to use a more complex DWARF expression for this
+ else if (regno == EXEC_HI_REG)
+ return 17; */
+ else if (regno == VCC_LO_REG)
+ return 768;
+ /* We need to use a more complex DWARF expression for this
+ else if (regno == VCC_HI_REG)
+ return 768; */
+ else if (regno == SCC_REG)
+ return 128;
+ else if (SGPR_REGNO_P (regno))
+ {
+ if (regno - FIRST_SGPR_REG < 64)
+ return (regno - FIRST_SGPR_REG + 32);
+ else
+ return (regno - FIRST_SGPR_REG + 1024);
+ }
+ else if (VGPR_REGNO_P (regno))
+ return (regno - FIRST_VGPR_REG + 2560);
+
+ /* Otherwise, there's nothing sensible to do. */
+ return regno + 100000;
+}
+
+/* Implement TARGET_DWARF_REGISTER_SPAN.
+
+ DImode and Vector DImode require additional registers. */
+
+static rtx
+gcn_dwarf_register_span (rtx rtl)
+{
+ machine_mode mode = GET_MODE (rtl);
+
+ if (VECTOR_MODE_P (mode))
+ mode = GET_MODE_INNER (mode);
+
+ if (GET_MODE_SIZE (mode) != 8)
+ return NULL_RTX;
+
+ rtx p = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
+ unsigned regno = REGNO (rtl);
+ XVECEXP (p, 0, 0) = gen_rtx_REG (SImode, regno);
+ XVECEXP (p, 0, 1) = gen_rtx_REG (SImode, regno + 1);
+
+ return p;
+}
+