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author
lkcl
<lkcl@web>
Fri, 26 Jul 2019 21:48:22 +0000
(22:48 +0100)
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IkiWiki
<ikiwiki.info>
Fri, 26 Jul 2019 21:48:22 +0000
(22:48 +0100)
simple_v_extension/abridged_spec.mdwn
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diff --git
a/simple_v_extension/abridged_spec.mdwn
b/simple_v_extension/abridged_spec.mdwn
index f2dff669e549aa8844302539532336257e09a5f8..53dda30b8109f46e38c63de84eb3affba5527b3e 100644
(file)
--- a/
simple_v_extension/abridged_spec.mdwn
+++ b/
simple_v_extension/abridged_spec.mdwn
@@
-13,6
+13,11
@@
Simple-V is a uniform parallelism API for RISC-V hardware that allows
the Program Counter to enter "sub-contexts" in which, ultimately, standard
RISC-V scalar opcodes are executed.
the Program Counter to enter "sub-contexts" in which, ultimately, standard
RISC-V scalar opcodes are executed.
+Regardless of the actual amount of hardware parallelism (if any is
+added at all by the implementor),
+in direct contrast to SIMD
+hardware parallelism is entirely transparent to software.
+
The sub-context execution is "nested" in "re-entrant" form, in the
following order:
The sub-context execution is "nested" in "re-entrant" form, in the
following order:
@@
-20,7
+25,7
@@
following order:
* VBLOCK sub-execution context (PCVBLK increments whilst PC is paused).
* VL element loops (STATE srcoffs and destoffs increment, PC and PCVBLK pause).
Predication bits may be individually applied per element.
* VBLOCK sub-execution context (PCVBLK increments whilst PC is paused).
* VL element loops (STATE srcoffs and destoffs increment, PC and PCVBLK pause).
Predication bits may be individually applied per element.
-* SUBVL element loops (STATE svdestoffs increments, VL pauses).
+*
Optional
SUBVL element loops (STATE svdestoffs increments, VL pauses).
Individual predicate bits from VL loops apply to the *group* of SUBVL
elements.
Individual predicate bits from VL loops apply to the *group* of SUBVL
elements.