+ (set_attr "type" "imul")])
+
+;
+; mulsidi3 instruction pattern(s).
+;
+
+;(define_expand "mulsidi3"
+; [(set (match_operand:DI 0 "register_operand" "")
+; (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
+; (sign_extend:DI (match_operand:SI 2 "general_operand" ""))))]
+; ""
+; "
+;{
+; emit_insn (gen_extendsidi2 (operands[0], operands[1]));
+; emit_insn (gen_muldisidi3 (operands[0], operands[0], operands[2]));
+; DONE;
+;}")
+
+;(define_insn "muldisidi3"
+; [(set (match_operand:DI 0 "register_operand" "=d,d")
+; (mult:DI (match_operand:DI 1 "register_operand" "0,0")
+; (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
+; (clobber (reg:CC 33))]
+; "!TARGET_64BIT"
+; "@
+; mr\\t%0,%2
+; m\\t%0,%2"
+; [(set_attr "op_type" "RR,RX")
+; (set_attr "atype" "reg,mem")
+; (set_attr "type" "imul")])