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permit MMIO loads to MSIP bit
author
Andrew Waterman
<andrew@sifive.com>
Tue, 21 Feb 2017 01:16:58 +0000
(17:16 -0800)
committer
Andrew Waterman
<andrew@sifive.com>
Tue, 21 Feb 2017 01:16:58 +0000
(17:16 -0800)
riscv/processor.cc
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diff --git
a/riscv/processor.cc
b/riscv/processor.cc
index ddef0e271c257106aca41ac6ff7cdf1a20ee453b..706c0bcd050f065bfde559b6ebb17981d115ea4e 100644
(file)
--- a/
riscv/processor.cc
+++ b/
riscv/processor.cc
@@
-684,6
+684,17
@@
void processor_t::register_base_instructions()
bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
{
bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
{
+ switch (addr)
+ {
+ case 0:
+ if (len <= 4) {
+ memset(bytes, 0, len);
+ bytes[0] = get_field(state.mip, MIP_MSIP);
+ return true;
+ }
+ break;
+ }
+
return false;
}
return false;
}
@@
-692,14
+703,14
@@
bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
switch (addr)
{
case 0:
switch (addr)
{
case 0:
- state.mip &= ~MIP_MSIP;
- if (bytes[0] & 1)
- state.mip |= MIP_MSIP;
- return true;
-
- default:
- return false;
+ if (len <= 4) {
+ state.mip = set_field(state.mip, MIP_MSIP, bytes[0]);
+ return true;
+ }
+ break;
}
}
+
+ return false;
}
void processor_t::trigger_updated()
}
void processor_t::trigger_updated()