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Make sure FP stores don't write memory if mstatus.FS=0.
author
Andrew Waterman
<waterman@cs.berkeley.edu>
Tue, 1 Nov 2016 07:34:54 +0000
(
00:34
-0700)
committer
Andrew Waterman
<waterman@cs.berkeley.edu>
Tue, 1 Nov 2016 07:35:17 +0000
(
00:35
-0700)
isa/rv64si/csr.S
patch
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diff --git
a/isa/rv64si/csr.S
b/isa/rv64si/csr.S
index 1f7bb7722a7b1a840c36118a03795bf23eac943e..13dbf2679545f9dda98bc74bad2d317486131c40 100644
(file)
--- a/
isa/rv64si/csr.S
+++ b/
isa/rv64si/csr.S
@@
-35,6
+35,19
@@
RVTEST_CODE_BEGIN
TEST_CASE( 9, a0, 0xbadbeef, csrr a0, sscratch);
#ifdef __MACHINE_MODE
TEST_CASE( 9, a0, 0xbadbeef, csrr a0, sscratch);
#ifdef __MACHINE_MODE
+ # Is F extension present?
+ csrr a0, misa
+ andi a0, a0, (1 << ('F' - 'A'))
+ beqz a0, 1f
+ # If so, make sure FP stores have no effect when mstatus.FS is off.
+ li a1, MSTATUS_FS
+ csrs mstatus, a1
+ fmv.s.x f0, x0
+ csrc mstatus, a1
+ la a1, fsw_data
+ TEST_CASE(10, a0, 1, fsw f0, (a1); lw a0, (a1));
+1:
+
# Figure out if 'U' is set in misa
csrr a0, misa # a0 = csr(misa)
srli a0, a0, 20 # a0 = a0 >> 20
# Figure out if 'U' is set in misa
csrr a0, misa # a0 = csr(misa)
srli a0, a0, 20 # a0 = a0 >> 20
@@
-53,15
+66,15
@@
RVTEST_CODE_BEGIN
# Make sure writing the cycle counter causes an exception.
# Don't run in supervisor, as we don't delegate illegal instruction traps.
#ifdef __MACHINE_MODE
# Make sure writing the cycle counter causes an exception.
# Don't run in supervisor, as we don't delegate illegal instruction traps.
#ifdef __MACHINE_MODE
- TEST_CASE(1
0
, a0, 255, li a0, 255; csrrw a0, cycle, x0);
+ TEST_CASE(1
1
, a0, 255, li a0, 255; csrrw a0, cycle, x0);
#endif
# Make sure reading status in user mode causes an exception.
# Don't run in supervisor, as we don't delegate illegal instruction traps.
#ifdef __MACHINE_MODE
#endif
# Make sure reading status in user mode causes an exception.
# Don't run in supervisor, as we don't delegate illegal instruction traps.
#ifdef __MACHINE_MODE
- TEST_CASE(1
1
, a0, 255, li a0, 255; csrr a0, sstatus)
+ TEST_CASE(1
2
, a0, 255, li a0, 255; csrr a0, sstatus)
#else
#else
- TEST_CASE(1
1
, x0, 0, nop)
+ TEST_CASE(1
2
, x0, 0, nop)
#endif
finish:
#endif
finish:
@@
-72,12
+85,13
@@
finish:
.align 2
stvec_handler:
.align 2
stvec_handler:
- # Trapping on tests 10
and 11
is good news.
+ # Trapping on tests 10
-12
is good news.
# Note that since the test didn't complete, TESTNUM is smaller by 1.
li t0, 9
# Note that since the test didn't complete, TESTNUM is smaller by 1.
li t0, 9
- beq TESTNUM, t0, privileged
- li t0, 10
- beq TESTNUM, t0, privileged
+ bltu TESTNUM, t0, 1f
+ li t0, 11
+ bleu TESTNUM, t0, privileged
+1:
# catch RVTEST_PASS and kick it up to M-mode
csrr t0, scause
# catch RVTEST_PASS and kick it up to M-mode
csrr t0, scause
@@
-101,6
+115,6
@@
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
.data
RVTEST_DATA_BEGIN
- TEST_DATA
+fsw_data: .word 1
RVTEST_DATA_END
RVTEST_DATA_END