+/**
+ * Update the cache coherency status of the batch to reflect a flush of the
+ * specified caching domain.
+ */
+static inline void
+iris_batch_mark_flush_sync(struct iris_batch *batch,
+ enum iris_domain access)
+{
+ batch->coherent_seqnos[access][access] = batch->next_seqno - 1;
+}
+
+/**
+ * Update the cache coherency status of the batch to reflect an invalidation
+ * of the specified caching domain. All prior flushes of other caches will be
+ * considered visible to the specified caching domain.
+ */
+static inline void
+iris_batch_mark_invalidate_sync(struct iris_batch *batch,
+ enum iris_domain access)
+{
+ for (unsigned i = 0; i < NUM_IRIS_DOMAINS; i++)
+ batch->coherent_seqnos[access][i] = batch->coherent_seqnos[i][i];
+}
+
+/**
+ * Update the cache coherency status of the batch to reflect a reset. All
+ * previously accessed data can be considered visible to every caching domain
+ * thanks to the kernel's heavyweight flushing at batch buffer boundaries.
+ */
+static inline void
+iris_batch_mark_reset_sync(struct iris_batch *batch)
+{
+ for (unsigned i = 0; i < NUM_IRIS_DOMAINS; i++)
+ for (unsigned j = 0; j < NUM_IRIS_DOMAINS; j++)
+ batch->coherent_seqnos[i][j] = batch->next_seqno - 1;
+}
+