projects
/
riscv-tests.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
|
inline
| side by side (parent:
208298c
)
Test debugging with/without a program buffer
author
Tim Newsome
<tim@sifive.com>
Mon, 19 Feb 2018 21:31:40 +0000
(13:31 -0800)
committer
Tim Newsome
<tim@sifive.com>
Thu, 1 Mar 2018 23:19:25 +0000
(15:19 -0800)
debug/Makefile
patch
|
blob
|
history
debug/targets/RISC-V/spike32-2-rtos.py
patch
|
blob
|
history
debug/targets/RISC-V/spike32-2.py
patch
|
blob
|
history
debug/targets/RISC-V/spike64.py
patch
|
blob
|
history
debug/testlib.py
patch
|
blob
|
history
diff --git
a/debug/Makefile
b/debug/Makefile
index 8e1c81b6bf67d2ab2673bbfedbf206675a16e2e0..48be07c45ae7663ffa4733cedca7393dedce9ac4 100644
(file)
--- a/
debug/Makefile
+++ b/
debug/Makefile
@@
-4,7
+4,7
@@
XLEN ?= 64
src_dir ?= .
GDBSERVER_PY = $(src_dir)/gdbserver.py
src_dir ?= .
GDBSERVER_PY = $(src_dir)/gdbserver.py
-default: spike$(XLEN)-2
+default: spike$(XLEN)
spike$(XLEN)
-2
all-tests: spike32 spike32-2 spike32-2-rtos spike64 spike64-2 spike64-2-rtos
all-tests: spike32 spike32-2 spike32-2-rtos spike64 spike64-2 spike64-2-rtos
diff --git
a/debug/targets/RISC-V/spike32-2-rtos.py
b/debug/targets/RISC-V/spike32-2-rtos.py
index a7b9a1c0a7a1b244afef8f4980554cbd8ec6b53c..79105d5f3a64ef1644843f1bdca0c598890edb85 100644
(file)
--- a/
debug/targets/RISC-V/spike32-2-rtos.py
+++ b/
debug/targets/RISC-V/spike32-2-rtos.py
@@
-9,4
+9,4
@@
class spike32_2(targets.Target):
timeout_sec = 30
def create(self):
timeout_sec = 30
def create(self):
- return testlib.Spike(self)
+ return testlib.Spike(self
, progbufsize=0
)
diff --git
a/debug/targets/RISC-V/spike32-2.py
b/debug/targets/RISC-V/spike32-2.py
index f57f816afeedaff230cb07aec4507a17c42ca733..89d3c2a3602bbc59bd96f92bdeda052df81d167d 100644
(file)
--- a/
debug/targets/RISC-V/spike32-2.py
+++ b/
debug/targets/RISC-V/spike32-2.py
@@
-9,4
+9,4
@@
class spike32_2(targets.Target):
timeout_sec = 30
def create(self):
timeout_sec = 30
def create(self):
- return testlib.Spike(self, isa="RV32IMAFC")
+ return testlib.Spike(self, isa="RV32IMAFC"
, progbufsize=0
)
diff --git
a/debug/targets/RISC-V/spike64.py
b/debug/targets/RISC-V/spike64.py
index 2aa1dd057ef66a9723f76c201763658604b3b409..d5802b5714c9e7443ec3e09151e981a95b917bc3 100644
(file)
--- a/
debug/targets/RISC-V/spike64.py
+++ b/
debug/targets/RISC-V/spike64.py
@@
-16,4
+16,4
@@
class spike64(targets.Target):
def create(self):
# 32-bit FPRs only
def create(self):
# 32-bit FPRs only
- return testlib.Spike(self, isa="RV64IMAFC")
+ return testlib.Spike(self, isa="RV64IMAFC"
, progbufsize=0
)
diff --git
a/debug/testlib.py
b/debug/testlib.py
index 3aaa542a5c76dce60bf92ca485119e2045b3dbe0..5c40a5dd135a116c639bd6ea3098c9aa904c3348 100644
(file)
--- a/
debug/testlib.py
+++ b/
debug/testlib.py
@@
-57,11
+57,12
@@
def compile(args, xlen=32): # pylint: disable=redefined-builtin
class Spike(object):
def __init__(self, target, halted=False, timeout=None, with_jtag_gdb=True,
class Spike(object):
def __init__(self, target, halted=False, timeout=None, with_jtag_gdb=True,
- isa=None):
+ isa=None
, progbufsize=None
):
"""Launch spike. Return tuple of its process and the port it's running
on."""
self.process = None
self.isa = isa
"""Launch spike. Return tuple of its process and the port it's running
on."""
self.process = None
self.isa = isa
+ self.progbufsize = progbufsize
if target.harts:
harts = target.harts
if target.harts:
harts = target.harts
@@
-118,6
+119,10
@@
class Spike(object):
cmd += ["--isa", isa]
cmd += ["--isa", isa]
+ if not self.progbufsize is None:
+ cmd += ["--progsize", str(self.progbufsize)]
+ cmd += ["--debug-sba", "32"]
+
assert len(set(t.ram for t in harts)) == 1, \
"All spike harts must have the same RAM layout"
assert len(set(t.ram_size for t in harts)) == 1, \
assert len(set(t.ram for t in harts)) == 1, \
"All spike harts must have the same RAM layout"
assert len(set(t.ram_size for t in harts)) == 1, \