-void evergreen_set_buffer_sync(
- struct r600_context *ctx,
- struct r600_resource* bo,
- int size,
- int flags,
- enum radeon_bo_usage usage)
-{
- assert(bo);
- int32_t cp_coher_size = 0;
-
- if (size == 0xffffffff || size == 0) {
- cp_coher_size = 0xffffffff;
- }
- else {
- cp_coher_size = ((size + 255) >> 8);
- }
-
- uint32_t sync_flags = 0;
-
- if ((flags & COMPUTE_RES_TC_FLUSH) == COMPUTE_RES_TC_FLUSH) {
- sync_flags |= S_0085F0_TC_ACTION_ENA(1);
- }
-
- if ((flags & COMPUTE_RES_VC_FLUSH) == COMPUTE_RES_VC_FLUSH) {
- sync_flags |= S_0085F0_VC_ACTION_ENA(1);
- }
-
- if ((flags & COMPUTE_RES_SH_FLUSH) == COMPUTE_RES_SH_FLUSH) {
- sync_flags |= S_0085F0_SH_ACTION_ENA(1);
- }
-
- if ((flags & COMPUTE_RES_CB_FLUSH(0)) == COMPUTE_RES_CB_FLUSH(0)) {
- sync_flags |= S_0085F0_CB_ACTION_ENA(1);
-
- switch((flags >> 8) & 0xF) {
- case 0:
- sync_flags |= S_0085F0_CB0_DEST_BASE_ENA(1);
- break;
- case 1:
- sync_flags |= S_0085F0_CB1_DEST_BASE_ENA(1);
- break;
- case 2:
- sync_flags |= S_0085F0_CB2_DEST_BASE_ENA(1);
- break;
- case 3:
- sync_flags |= S_0085F0_CB3_DEST_BASE_ENA(1);
- break;
- case 4:
- sync_flags |= S_0085F0_CB4_DEST_BASE_ENA(1);
- break;
- case 5:
- sync_flags |= S_0085F0_CB5_DEST_BASE_ENA(1);
- break;
- case 6:
- sync_flags |= S_0085F0_CB6_DEST_BASE_ENA(1);
- break;
- case 7:
- sync_flags |= S_0085F0_CB7_DEST_BASE_ENA(1);
- break;
- case 8:
- sync_flags |= S_0085F0_CB8_DEST_BASE_ENA(1);
- break;
- case 9:
- sync_flags |= S_0085F0_CB9_DEST_BASE_ENA(1);
- break;
- case 10:
- sync_flags |= S_0085F0_CB10_DEST_BASE_ENA(1);
- break;
- case 11:
- sync_flags |= S_0085F0_CB11_DEST_BASE_ENA(1);
- break;
- default:
- assert(0);
- }
- }
-
- int32_t poll_interval = 10;
-
- ctx->cs->buf[ctx->cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
- ctx->cs->buf[ctx->cs->cdw++] = sync_flags;
- ctx->cs->buf[ctx->cs->cdw++] = cp_coher_size;
- ctx->cs->buf[ctx->cs->cdw++] = 0;
- ctx->cs->buf[ctx->cs->cdw++] = poll_interval;
-
- if (cp_coher_size != 0xffffffff) {
- evergreen_emit_ctx_reloc(ctx, bo, usage);
- }
-}
-