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update README
master
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sun, 27 Feb 2022 11:56:39 +0000
(11:56 +0000)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sun, 27 Feb 2022 11:56:39 +0000
(11:56 +0000)
README.txt
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diff --git
a/README.txt
b/README.txt
index 4dd5e0d4fc8416b4cdc6e0e5ca7c899ec2aef2c9..3b73058b162bd27a65918c9f9605e133f8f65ab0 100644
(file)
--- a/
README.txt
+++ b/
README.txt
@@
-1,24
+1,37
@@
# sim openocd test
in the soc directory, create the verilog file
# sim openocd test
in the soc directory, create the verilog file
+
"python issuer_verilog.py libresoc.v"
"python issuer_verilog.py libresoc.v"
-copy to libresoc/ directory
-terminal 1: ./sim.py
-terminal 2: openocd -f openocd.cfg -c init -c 'svf idcode_test2.svf'
+copy to libresoc/ directory and open a second terminal
+
+terminal 1:
+
+ ./sim.py
+
+terminal 2:
+
+ openocd -f openocd.cfg -c init -c 'svf idcode_test2.svf'
# ecp5 build
same thing: first build libresoc.v and copy it to the libresoc/ directory
# ecp5 build
same thing: first build libresoc.v and copy it to the libresoc/ directory
-./versa_ecp5.py --sys-clk-freq=55e6 --build --yosys-nowidelut
-./versa_ecp5.py --sys-clk-freq=55e6 --load
+ ./versa_ecp5.py --sys-clk-freq=55e6 --build --yosys-nowidelut
+ ./versa_ecp5.py --sys-clk-freq=55e6 --load
+
+ulx3s:
+
+ ./versa_ecp5.py --sys-clk-freq=12.5e6 --build --fpga=ulx3s85f \
+ --yosys-nowidelut
+ ./versa_ecp5.py --sys-clk-freq=12.5e6 --load --fpga=ulx3s85f
# arty a7 build
# arty a7 build
-export PATH=$PATH:/usr/local/symbiflow/bin/:/usr/local/symbiflow/vtr/bin/
-./versa_ecp5.py --sys-clk-freq=25e6 --build --fpga=artya7100t \
- --toolchain=symbiflow
-./versa_ecp5.py --sys-clk-freq=25e6 --load --fpga=artya7100t \
- --toolchain=symbiflow
+
export PATH=$PATH:/usr/local/symbiflow/bin/:/usr/local/symbiflow/vtr/bin/
+
./versa_ecp5.py --sys-clk-freq=25e6 --build --fpga=artya7100t \
+
--toolchain=symbiflow
+
./versa_ecp5.py --sys-clk-freq=25e6 --load --fpga=artya7100t \
+
--toolchain=symbiflow