soc/integration/csr_bridge: use registered version only when SDRAM is present.

Seems to be a good compromise for now.

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index ad216377ac3ede7674dd95c55427b38aa5c39085..54f969c918abc32be5e900980344637446bbd3a9 100644 (file)
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -803,7 +803,7 @@ class SoC(Module):
     def add_rom(self, name, origin, size, contents=[]):
         self.add_ram(name, origin, size, contents, mode="r")
 
     def add_rom(self, name, origin, size, contents=[]):
         self.add_ram(name, origin, size, contents, mode="r")
 

-    def add_csr_bridge(self, origin):
+    def add_csr_bridge(self, origin, register=False):

         csr_bridge_cls = {
             "wishbone": wishbone.Wishbone2CSR,
             "axi-lite": axi.AXILite2CSR,
         csr_bridge_cls = {
             "wishbone": wishbone.Wishbone2CSR,
             "axi-lite": axi.AXILite2CSR,


@@ -811,7 +811,8 @@ class SoC(Module):
         self.submodules.csr_bridge = csr_bridge_cls(
             bus_csr       = csr_bus.Interface(
             address_width = self.csr.address_width,
         self.submodules.csr_bridge = csr_bridge_cls(
             bus_csr       = csr_bus.Interface(
             address_width = self.csr.address_width,

-            data_width    = self.csr.data_width))
+            data_width    = self.csr.data_width),
+            register = register)

         csr_size   = 2**(self.csr.address_width + 2)
         csr_region = SoCRegion(origin=origin, size=csr_size, cached=False)
         bus = getattr(self.csr_bridge, self.bus.standard.replace('-', '_'))
         csr_size   = 2**(self.csr.address_width + 2)
         csr_region = SoCRegion(origin=origin, size=csr_size, cached=False)
         bus = getattr(self.csr_bridge, self.bus.standard.replace('-', '_'))


@@ -910,6 +911,10 @@ class SoC(Module):
             "axi-lite": axi.AXILiteInterconnectShared,
         }[self.bus.standard]
 
             "axi-lite": axi.AXILiteInterconnectShared,
         }[self.bus.standard]
 

+        # SoC CSR bridge ---------------------------------------------------------------------------
+        # FIXME: for now, use registered CSR bridge when SDRAM is present; find the best compromise.
+        self.add_csr_bridge(self.mem_map["csr"], register=hasattr(self, "sdram"))
+

         # SoC Bus Interconnect ---------------------------------------------------------------------
         if len(self.bus.masters) and len(self.bus.slaves):
             # If 1 bus_master, 1 bus_slave and no address translation, use InterconnectPointToPoint.
         # SoC Bus Interconnect ---------------------------------------------------------------------
         if len(self.bus.masters) and len(self.bus.slaves):
             # If 1 bus_master, 1 bus_slave and no address translation, use InterconnectPointToPoint.

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 281f34e4e12723d054e6a2fae2aa3e525774ab2b..6074132225ed1dcd4c7438fe327aada32d8e3939 100644 (file)
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -187,9 +187,6 @@ class SoCCore(LiteXSoC):
             if timer_uptime:
                 self.timer0.add_uptime()
 
             if timer_uptime:
                 self.timer0.add_uptime()
 

-        # Add CSR bridge
-        self.add_csr_bridge(self.mem_map["csr"])
-

     # Methods --------------------------------------------------------------------------------------
 
     def add_interrupt(self, interrupt_name, interrupt_id=None, use_loc_if_exists=False):
     # Methods --------------------------------------------------------------------------------------
 
     def add_interrupt(self, interrupt_name, interrupt_id=None, use_loc_if_exists=False):