create Port class and remove connect method of mac/ip/udp Ports

diff --git a/liteeth/common.py b/liteeth/common.py
index ce7e0d6334f62f9c73a4b20257cd9405ea262a76..6ac03099ca5489c6103beae1c632ce3dfd50fd36 100644 (file)
--- a/liteeth/common.py
+++ b/liteeth/common.py
@@ -252,6 +252,15 @@ def eth_etherbone_user_description(dw):
        return EndpointDescription(payload_layout, param_layout, packetized=True)
 
 
+# Generic classes
+class Port:
+       def connect(self, port):
+               r = [
+                       Record.connect(self.source, port.sink),
+                       Record.connect(port.source, self.sink)
+               ]
+               return r
+
 # Generic modules
 @DecorateModule(InsertReset)
 @DecorateModule(InsertCE)

diff --git a/liteeth/core/ip/common.py b/liteeth/core/ip/common.py
index 338033ea6b4e5246799fead2f3ed71d3f3b86cb1..17102767dbbf734a86735be59c5af7081b6344d0 100644 (file)
--- a/liteeth/core/ip/common.py
+++ b/liteeth/core/ip/common.py
@@ -25,24 +25,12 @@ class LiteEthIPV4MasterPort:
                self.source = Source(eth_ipv4_user_description(dw))
                self.sink = Sink(eth_ipv4_user_description(dw))
 
-       def connect(self, slave):
-               return [
-                       Record.connect(self.source, slave.sink),
-                       Record.connect(slave.source, self.sink)
-               ]
-
 class LiteEthIPV4SlavePort:
        def __init__(self, dw):
                self.dw = dw
                self.sink = Sink(eth_ipv4_user_description(dw))
                self.source = Source(eth_ipv4_user_description(dw))
 
-       def connect(self, master):
-               return [
-                       Record.connect(self.sink, master.source),
-                       Record.connect(master.sink, self.source)
-               ]
-
 class LiteEthIPV4UserPort(LiteEthIPV4SlavePort):
        def __init__(self, dw):
                LiteEthIPV4SlavePort.__init__(self, dw)

diff --git a/liteeth/core/udp/common.py b/liteeth/core/udp/common.py
index 98fe9be361cdd3297e7aa07151a40b9658fb10d6..187b829e441ff9945829efb7f59dc3bccbc295df 100644 (file)
--- a/liteeth/core/udp/common.py
+++ b/liteeth/core/udp/common.py
@@ -25,24 +25,12 @@ class LiteEthUDPMasterPort:
                self.source = Source(eth_udp_user_description(dw))
                self.sink = Sink(eth_udp_user_description(dw))
 
-       def connect(self, slave):
-               return [
-                       Record.connect(self.source, slave.sink),
-                       Record.connect(slave.source, self.sink)
-               ]
-
 class LiteEthUDPSlavePort:
        def __init__(self, dw):
                self.dw =dw
                self.sink = Sink(eth_udp_user_description(dw))
                self.source = Source(eth_udp_user_description(dw))
 
-       def connect(self, master):
-               return [
-                       Record.connect(self.sink, master.source),
-                       Record.connect(master.sink, self.source)
-               ]
-
 class LiteEthUDPUserPort(LiteEthUDPSlavePort):
        def __init__(self, dw):
                LiteEthUDPSlavePort.__init__(self, dw)

diff --git a/liteeth/mac/__init__.py b/liteeth/mac/__init__.py
index e7bf6d66c91da164ee1ec3224098727bf3bccbf3..2346584e402fde9e3a62761338f4f79060276255 100644 (file)
--- a/liteeth/mac/__init__.py
+++ b/liteeth/mac/__init__.py
@@ -20,10 +20,7 @@ class LiteEthMAC(Module, AutoCSR):
                        ]
                elif interface == "wishbone":
                        self.submodules.interface = LiteEthMACWishboneInterface(dw, 2, 2)
-                       self.comb += [
-                               Record.connect(self.interface.source, self.core.sink),
-                               Record.connect(self.core.source, self.interface.sink)
-                       ]
+                       self.comb += Port.connect(self.interface, self.core)
                        self.ev, self.bus = self.interface.sram.ev, self.interface.bus
                        self.csrs = self.interface.get_csrs()
                elif interface == "dma":

diff --git a/liteeth/mac/common.py b/liteeth/mac/common.py
index f82faecb9e595140107dc2dd37e6366ee8f5da04..128d8f17cf18a039ff424fffe6d9c07dca036e47 100644 (file)
--- a/liteeth/mac/common.py
+++ b/liteeth/mac/common.py
@@ -24,23 +24,11 @@ class LiteEthMACMasterPort:
                self.source = Source(eth_mac_description(dw))
                self.sink = Sink(eth_mac_description(dw))
 
-       def connect(self, slave):
-               return [
-                       Record.connect(self.source, slave.sink),
-                       Record.connect(slave.source, self.sink)
-               ]
-
 class LiteEthMACSlavePort:
        def __init__(self, dw):
                self.sink = Sink(eth_mac_description(dw))
                self.source = Source(eth_mac_description(dw))
 
-       def connect(self, master):
-               return [
-                       Record.connect(self.sink, master.source),
-                       Record.connect(master.sink, self.source)
-               ]
-
 class LiteEthMACUserPort(LiteEthMACSlavePort):
        def __init__(self, dw):
                LiteEthMACSlavePort.__init__(self, dw)