Add more entries
authorEddie Hung <eddie@fpgeh.com>
Thu, 19 Sep 2019 19:00:39 +0000 (12:00 -0700)
committerEddie Hung <eddie@fpgeh.com>
Thu, 19 Sep 2019 19:00:39 +0000 (12:00 -0700)
CHANGELOG

index 8d7dd3e191f62c3fb08cc4c7f7a92f83009741b6..8ee73771f351e1ec1c7a2173da5032061f6ba990 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -41,6 +41,7 @@ Yosys 0.9 .. Yosys 0.9-dev
     - Added "_TECHMAP_WIREINIT_*_" attribute and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
     - Added "-match-init" option to "dff2dffs" pass
     - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
+    - Added "ice40_dsp" for Lattice iCE40 DSP packing
     - Added "xilinx_dsp" for Xilinx DSP packing
     - "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
     - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)