* alpha.h (PRINT_OPERAND_PUNCT_VALID_P): Accept '(' for s/sv/svi.
* alpha.c (print_operand): Handle it.
* alpha.md (fix_truncsfdi2): Use it. Add earlyclobber pattern
for ALPHA_TP_INSN.
(fix_truncdfdi2): Likewise.
From-SVN: r18996
+Sat Apr 4 18:07:16 1998 David Mosberger-Tang (davidm@mostang.com)
+
+ * alpha.h (PRINT_OPERAND_PUNCT_VALID_P): Accept '(' for s/sv/svi.
+ * alpha.c (print_operand): Handle it.
+ * alpha.md (fix_truncsfdi2): Use it. Add earlyclobber pattern
+ for ALPHA_TP_INSN.
+ (fix_truncdfdi2): Likewise.
+
Sat Apr 4 17:42:05 1998 Richard Henderson <rth@cygnus.com>
* tree.h (sizetype_tab[2], sbitsizetype, ubitsizetype): Merge all
fputs ("su", file);
break;
+ case '(':
+ /* Generates trap-mode suffix for instructions that accept the
+ v, sv, and svi suffix. The only instruction that needs this
+ is cvttq. */
+ switch (alpha_fptm)
+ {
+ case ALPHA_FPTM_N:
+ case ALPHA_FPTM_U:
+ fputs ("v", file);
+ break;
+ case ALPHA_FPTM_SU:
+ fputs ("sv", file);
+ break;
+ case ALPHA_FPTM_SUI:
+ fputs ("svi", file);
+ break;
+ }
+ break;
+
case ')':
/* Generates trap-mode suffix for instructions that accept the u, su,
and sui suffix. This is the bulk of the IEEE floating point
' Generates trap-mode suffix for instructions that accept the
su suffix only (cmpt et al).
+ ( Generates trap-mode suffix for instructions that accept the
+ v, sv, and svi suffix. The only instruction that needs this
+ is cvttq.
+
) Generates trap-mode suffix for instructions that accept the
u, su, and sui suffix. This is the bulk of the IEEE floating
point instructions (addt et al).
*/
#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
- ((CODE) == '&' || (CODE) == '\'' || (CODE) == ')' || (CODE) == '+' \
- || (CODE) == ',' || (CODE) == '-')
+ ((CODE) == '&' || (CODE) == '\'' || (CODE) == '(' || (CODE) == ')' \
+ || (CODE) == '+' || (CODE) == ',' || (CODE) == '-')
\f
/* Print a memory address as an operand to reference that memory location. */
[(set_attr "type" "fadd")
(set_attr "trap" "yes")])
+(define_insn ""
+ [(set (match_operand:DI 0 "register_operand" "=&f")
+ (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
+ "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
+ "cvt%-q%(c %R1,%0"
+ [(set_attr "type" "fadd")
+ (set_attr "trap" "yes")])
+
(define_insn "fix_truncdfdi2"
[(set (match_operand:DI 0 "register_operand" "=f")
(fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
"TARGET_FP"
- "cvt%-qc %R1,%0"
- [(set_attr "type" "fadd")])
+ "cvt%-q%(c %R1,%0"
+ [(set_attr "type" "fadd")
+ (set_attr "trap" "yes")])
+
+(define_insn ""
+ [(set (match_operand:DI 0 "register_operand" "=&f")
+ (fix:DI (float_extend:DF
+ (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
+ "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
+ "cvt%-q%(c %R1,%0"
+ [(set_attr "type" "fadd")
+ (set_attr "trap" "yes")])
(define_insn "fix_truncsfdi2"
[(set (match_operand:DI 0 "register_operand" "=f")
(fix:DI (float_extend:DF
(match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
"TARGET_FP"
- "cvt%-qc %R1,%0"
- [(set_attr "type" "fadd")])
+ "cvt%-q%(c %R1,%0"
+ [(set_attr "type" "fadd")
+ (set_attr "trap" "yes")])
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=&f")