#define ISA_HAS_CONDMOVE (mips_isa == 4 \
)
+/* ISA has just the integer condition move instructions (movn,movz) */
+#define ISA_HAS_INT_CONDMOVE 0
+
+
+
/* ISA has the mips4 FP condition code instructions: FP-compare to CC,
branch on CC, and move (both FP and non-FP) on CC. */
#define ISA_HAS_8CC (mips_isa == 4 \
;; Mips.md Machine Description for MIPS based processors
-;; Copyright (C) 1989, 90-98, 1999 Free Software Foundation, Inc.
+;; Copyright (C) 1989, 90-98, 1999, 2000 Free Software Foundation, Inc.
;; Contributed by A. Lichnewsky, lich@inria.inria.fr
;; Changes by Michael Meissner, meissner@osf.org
;; 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
(const_int 0)])
(match_operand:SI 2 "reg_or_0_operand" "dJ,0")
(match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
- "ISA_HAS_CONDMOVE"
+ "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
"@
mov%B4\\t%0,%z2,%1
mov%b4\\t%0,%z3,%1"
(const_int 0)])
(match_operand:SI 2 "reg_or_0_operand" "dJ,0")
(match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
- "ISA_HAS_CONDMOVE"
+ "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
"@
mov%B4\\t%0,%z2,%1
mov%b4\\t%0,%z3,%1"
(const_int 0)])
(match_operand:DI 2 "se_reg_or_0_operand" "dJ,0")
(match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))]
- "ISA_HAS_CONDMOVE"
+ "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
"@
mov%B4\\t%0,%z2,%1
mov%b4\\t%0,%z3,%1"
(const_int 0)])
(match_operand:DI 2 "se_reg_or_0_operand" "dJ,0")
(match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))]
- "ISA_HAS_CONDMOVE"
+ "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
"@
mov%B4\\t%0,%z2,%1
mov%b4\\t%0,%z3,%1"
(if_then_else:SI (match_dup 5)
(match_operand:SI 2 "reg_or_0_operand" "")
(match_operand:SI 3 "reg_or_0_operand" "")))]
- "ISA_HAS_CONDMOVE"
+ "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
"
{
gen_conditional_move (operands);
(if_then_else:DI (match_dup 5)
(match_operand:DI 2 "se_reg_or_0_operand" "")
(match_operand:DI 3 "se_reg_or_0_operand" "")))]
- "ISA_HAS_CONDMOVE"
+ "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
"
{
gen_conditional_move (operands);