sce*test*_out_dif.dat : Change the last line of the files to be
authorJillian Ye <jillian@cygnus>
Wed, 29 Apr 1998 00:48:13 +0000 (00:48 +0000)
committerJillian Ye <jillian@cygnus>
Wed, 29 Apr 1998 00:48:13 +0000 (00:48 +0000)
                         "7f 00000000 00000000"
: ----------------------------------------------------------------------

61 files changed:
sim/testsuite/sky/Makefile.in
sim/testsuite/sky/sce2_test11_out_gif.dat
sim/testsuite/sky/sce2_test12_out_gif.dat
sim/testsuite/sky/sce2_test23_out_gif.dat
sim/testsuite/sky/sce_test10_out_gif.dat
sim/testsuite/sky/sce_test13_out_gif.dat
sim/testsuite/sky/sce_test14_out_gif.dat
sim/testsuite/sky/sce_test15_out_gif.dat
sim/testsuite/sky/sce_test16_out_gif.dat
sim/testsuite/sky/sce_test17_out_gif.dat
sim/testsuite/sky/sce_test18_out_gif.dat
sim/testsuite/sky/sce_test19_out_gif.dat
sim/testsuite/sky/sce_test1_out_gif.dat
sim/testsuite/sky/sce_test20_out_gif.dat
sim/testsuite/sky/sce_test21_out_gif.dat
sim/testsuite/sky/sce_test22_out_gif.dat
sim/testsuite/sky/sce_test24_out_gif.dat
sim/testsuite/sky/sce_test25_out_gif.dat
sim/testsuite/sky/sce_test26_out_gif.dat
sim/testsuite/sky/sce_test27_out_gif.dat
sim/testsuite/sky/sce_test28_out_gif.dat
sim/testsuite/sky/sce_test29_out_gif.dat
sim/testsuite/sky/sce_test2_out_gif.dat
sim/testsuite/sky/sce_test30_out_gif.dat
sim/testsuite/sky/sce_test31_out_gif.dat
sim/testsuite/sky/sce_test32_out_gif.dat
sim/testsuite/sky/sce_test33_out_gif.dat
sim/testsuite/sky/sce_test34_out_gif.dat
sim/testsuite/sky/sce_test35_out_gif.dat
sim/testsuite/sky/sce_test36_out_gif.dat
sim/testsuite/sky/sce_test37_out_gif.dat
sim/testsuite/sky/sce_test38_out_gif.dat
sim/testsuite/sky/sce_test39_out_gif.dat
sim/testsuite/sky/sce_test3_out_gif.dat
sim/testsuite/sky/sce_test40_out_gif.dat
sim/testsuite/sky/sce_test41_out_gif.dat
sim/testsuite/sky/sce_test42_out_gif.dat
sim/testsuite/sky/sce_test43_out_gif.dat
sim/testsuite/sky/sce_test44_out_gif.dat
sim/testsuite/sky/sce_test45_out_gif.dat
sim/testsuite/sky/sce_test46_out_gif.dat
sim/testsuite/sky/sce_test47_out_gif.dat
sim/testsuite/sky/sce_test48_out_gif.dat
sim/testsuite/sky/sce_test49_out_gif.dat
sim/testsuite/sky/sce_test4_out_gif.dat
sim/testsuite/sky/sce_test50_out_gif.dat
sim/testsuite/sky/sce_test51_out_gif.dat
sim/testsuite/sky/sce_test52_out_gif.dat
sim/testsuite/sky/sce_test53_out_gif.dat
sim/testsuite/sky/sce_test54_out_gif.dat
sim/testsuite/sky/sce_test55_out_gif.dat
sim/testsuite/sky/sce_test56_out_gif.dat
sim/testsuite/sky/sce_test57_out_gif.dat
sim/testsuite/sky/sce_test58_out_gif.dat
sim/testsuite/sky/sce_test59_out_gif.dat
sim/testsuite/sky/sce_test5_out_gif.dat
sim/testsuite/sky/sce_test6_out_gif.dat
sim/testsuite/sky/sce_test7_out_gif.dat
sim/testsuite/sky/sce_test8_out_gif.dat
sim/testsuite/sky/sce_test9_out_gif.dat
sim/testsuite/sky/t-dma.dmaexpect [new file with mode: 0644]

index 97ee30953fef68045ae34bc4929134e69e24b6ce..45ab8401f894f479dd670e85cf76b92abd4ef50e 100644 (file)
@@ -163,7 +163,7 @@ sce%.exe: sce%.o sce_main.o refresh.o
 sce_main.o: sce_main.c
        $(GCC_FOR_TARGET) -c $(CFLAGS) -o $@ $<
 
-refresh.o: refresh.s
+refresh.o: refresh.dvpasm
        $(DVPAS_FOR_TARGET) $(ASFLAGS) -o $@ $<
 
 sce_%.o: sce_%.dvpasm sce_%.vuasm
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 04 01032952 80007f4d
-7f 000000000 00000000
+7f 00000000 00000000
index 4c260d32224b94d1df8224d36cd098218b226e27..8c116df1867bfa7c7c5aed3b1731d8b3e7dead8b 100644 (file)
 04 0197b629 7fd68423
 01 3f800000 00545454
 04 0095e7b4 7f998440
-7f 000000000 00000000
+7f 00000000 00000000
index f718b2c31e8d249f2fd90acccac568056fef4b94..491f1ca0abcecc2f3ebdf9d923933d10e2f5c430 100644 (file)
 04 00998017 80128401
 01 3f800000 003f3f3f
 04 0095f452 7f998448
-7f 000000000 00000000
+7f 00000000 00000000
index b26a00515f848f2a0c14d96860c28826074328d3..37f66b141aa669c9c7ed4344d59613171c17b1f3 100644 (file)
 04 01996cdc 801283fa
 01 3f800000 00575757
 04 0095e7b4 7f998440
-7f 000000000 00000000
+7f 00000000 00000000
index 8873af9d046a3959c2d9b340b27ccb5be6605079..5abfe6351bfbd08de27d9744af808c0a2d71133e 100644 (file)
 04 01996cdc 801283fa
 01 3f800000 00575757
 04 0095e7b4 7f998440
-7f 000000000 00000000
+7f 00000000 00000000
diff --git a/sim/testsuite/sky/t-dma.dmaexpect b/sim/testsuite/sky/t-dma.dmaexpect
new file mode 100644 (file)
index 0000000..da15c62
--- /dev/null
@@ -0,0 +1,118 @@
+Testing DMA_D_CTRL...
+Testing DMA_D_STAT...
+DMA warning: write reg 0x1000e010 req=0xffffffff actual=0x63ffe3ff
+Testing DMA_D_PCR...
+DMA warning: write reg 0x1000e020 req=0x8fff0000 actual=0x83ff0000
+DMA warning: write reg 0x1000e020 req=0x05550000 actual=0x01550000
+DMA warning: write reg 0x1000e020 req=0x0155aaaa actual=0x015502aa
+DMA warning: write reg 0x1000e020 req=0x00005555 actual=0x00000155
+Testing DMA_D_SQWC...
+DMA warning: read from unsupported register (D_SQWC)
+DMA warning: write reg 0x1000e030 req=0x5555aaaa actual=0x005500aa
+DMA warning: write to unsupported register (D_SQWC)
+DMA warning: read from unsupported register (D_SQWC)
+DMA warning: write reg 0x1000e030 req=0xaaaa5555 actual=0x00aa0055
+DMA warning: write to unsupported register (D_SQWC)
+DMA warning: read from unsupported register (D_SQWC)
+DMA warning: write to unsupported register (D_SQWC)
+Testing DMA_D_RBOR...
+DMA warning: read from unsupported register (D_RBOR)
+DMA warning: write reg 0x1000e050 req=0x5555aaaa actual=0x5555aaa0
+DMA warning: write to unsupported register (D_RBOR)
+DMA warning: read from unsupported register (D_RBOR)
+DMA warning: write reg 0x1000e050 req=0xaaaa5555 actual=0x2aaa5550
+DMA warning: write to unsupported register (D_RBOR)
+DMA warning: read from unsupported register (D_RBOR)
+DMA warning: write to unsupported register (D_RBOR)
+Testing DMA_D_RBSR...
+DMA warning: read from unsupported register (D_RBSR)
+DMA warning: write reg 0x1000e040 req=0x5555aaaa actual=0x5555aaa0
+DMA warning: write to unsupported register (D_RBSR)
+DMA warning: read from unsupported register (D_RBSR)
+DMA warning: write reg 0x1000e040 req=0xaaaa5555 actual=0x2aaa5550
+DMA warning: write to unsupported register (D_RBSR)
+DMA warning: read from unsupported register (D_RBSR)
+DMA warning: write to unsupported register (D_RBSR)
+Testing DMA_D_STADR...
+DMA warning: read from unsupported register (D_STADR)
+DMA warning: write reg 0x1000e060 req=0x5555aaaa actual=0x5555aaa0
+DMA warning: write to unsupported register (D_STADR)
+DMA warning: read from unsupported register (D_STADR)
+DMA warning: write reg 0x1000e060 req=0xaaaa5555 actual=0x2aaa5550
+DMA warning: write to unsupported register (D_STADR)
+DMA warning: read from unsupported register (D_STADR)
+DMA warning: write to unsupported register (D_STADR)
+Testing DMA_D0_CHCR...
+DMA warning: write reg 0x10008000 req=0x5555aaaa actual=0x000000aa
+DMA warning: write reg 0x10008000 req=0xaaaa5555 actual=0x00000155
+Testing DMA_D0_MADR...
+DMA warning: write reg 0x10008010 req=0x5555aaaa actual=0x5555aaa0
+DMA warning: write reg 0x10008010 req=0x2aaa5555 actual=0x2aaa5550
+Testing DMA_D0_TADR...
+DMA warning: write reg 0x10008030 req=0x5555aaaa actual=0x5555aaa0
+DMA warning: write reg 0x10008030 req=0x2aaa5555 actual=0x2aaa5550
+Testing DMA_D0_ASR0...
+DMA warning: write reg 0x10008040 req=0x5555aaaa actual=0x5555aaa0
+DMA warning: write reg 0x10008040 req=0x2aaa5555 actual=0x2aaa5550
+Testing DMA_D0_ASR1...
+DMA warning: write reg 0x10008050 req=0x5555aaaa actual=0x5555aaa0
+DMA warning: write reg 0x10008050 req=0x2aaa5555 actual=0x2aaa5550
+Testing DMA_D0_QWC...
+DMA warning: write reg 0x10008020 req=0x5555aaaa actual=0x0000aaaa
+DMA warning: write reg 0x10008020 req=0xaaaa5555 actual=0x00005555
+Testing DMA_D0_PKTFLAG...
+Testing DMA_D1_CHCR...
+DMA warning: write reg 0x10009000 req=0x5555aaaa actual=0x000000aa
+DMA warning: write reg 0x10009000 req=0xaaaa5555 actual=0x00000155
+Testing DMA_D1_MADR...
+DMA warning: write reg 0x10009010 req=0x5555aaaa actual=0x5555aaa0
+DMA warning: write reg 0x10009010 req=0x2aaa5555 actual=0x2aaa5550
+Testing DMA_D1_TADR...
+DMA warning: write reg 0x10009030 req=0x5555aaaa actual=0x5555aaa0
+DMA warning: write reg 0x10009030 req=0x2aaa5555 actual=0x2aaa5550
+Testing DMA_D1_ASR0...
+DMA warning: write reg 0x10009040 req=0x5555aaaa actual=0x5555aaa0
+DMA warning: write reg 0x10009040 req=0x2aaa5555 actual=0x2aaa5550
+Testing DMA_D1_ASR1...
+DMA warning: write reg 0x10009050 req=0x5555aaaa actual=0x5555aaa0
+DMA warning: write reg 0x10009050 req=0x2aaa5555 actual=0x2aaa5550
+Testing DMA_D1_QWC...
+DMA warning: write reg 0x10009020 req=0x5555aaaa actual=0x0000aaaa
+DMA warning: write reg 0x10009020 req=0xaaaa5555 actual=0x00005555
+Testing DMA_D1_PKTFLAG...
+Testing DMA_D2_CHCR...
+DMA warning: write reg 0x1000a000 req=0x5555aaaa actual=0x000000aa
+DMA warning: write reg 0x1000a000 req=0xaaaa5555 actual=0x00000155
+Testing DMA_D2_MADR...
+DMA warning: write reg 0x1000a010 req=0x5555aaaa actual=0x5555aaa0
+DMA warning: write reg 0x1000a010 req=0x2aaa5555 actual=0x2aaa5550
+Testing DMA_D2_TADR...
+DMA warning: write reg 0x1000a030 req=0x5555aaaa actual=0x5555aaa0
+DMA warning: write reg 0x1000a030 req=0x2aaa5555 actual=0x2aaa5550
+Testing DMA_D2_ASR0...
+DMA warning: write reg 0x1000a040 req=0x5555aaaa actual=0x5555aaa0
+DMA warning: write reg 0x1000a040 req=0x2aaa5555 actual=0x2aaa5550
+Testing DMA_D2_ASR1...
+DMA warning: write reg 0x1000a050 req=0x5555aaaa actual=0x5555aaa0
+DMA warning: write reg 0x1000a050 req=0x2aaa5555 actual=0x2aaa5550
+Testing DMA_D2_QWC...
+DMA warning: write reg 0x1000a020 req=0x5555aaaa actual=0x0000aaaa
+DMA warning: write reg 0x1000a020 req=0xaaaa5555 actual=0x00005555
+Testing DMA_D2_PKTFLAG...
+
+Preparing for a DMA1 NORM transfer...
+Ready...
+Completed OK...
+
+Preparing for a DMA0 TAG transfer...
+Ready...
+DMA WARNING: address in tag (0x0001ad41_0c000001) is not quad word aligned.
+Completed OK...
+
+Preparing for a DMA2 TAG transfer with suspension...
+Ready...
+DMA WARNING: address in tag (0x0001ad41_0c000001) is not quad word aligned.
+returns...
+Suspended OK...
+DMA warning: write reg 0x1000a000 req=0xb0000104 actual=0x00000104
+Completed OK...