Fix test using delays for comb propagation instead of additional clock pulses

diff --git a/gram/test/test_core_refresher.py b/gram/test/test_core_refresher.py
index 7460442edcfb705ed91b0352d3788772b56f1b08..6c924d1727364a031869d9ea64295b594d62d97e 100644 (file)
--- a/gram/test/test_core_refresher.py
+++ b/gram/test/test_core_refresher.py
@@ -13,11 +13,11 @@ class RefreshExecuterTestCase(FHDLTestCase):
 
             def process():
                 yield dut.start.eq(1)
-                yield
-                yield
+                yield; yield Delay(1e-8)
                 self.assertEqual((yield dut.a), 2**10)
                 for i in range(trp):
                     yield
+                yield Delay(1e-8)
                 self.assertEqual((yield dut.a), 0)
 
             runSimulation(dut, process, "test_refreshexecuter.vcd")
@@ -77,8 +77,7 @@ class RefreshPostponerTestCase(FHDLTestCase):
                     yield
 
                 yield dut.req_i.eq(0)
-                yield
-                yield
+                yield; yield Delay(1e-8)
 
                 self.assertFalse((yield dut.req_o))