ARM: Flesh out 32 bit thumb load word decoding.

diff --git a/src/arch/arm/isa/bitfields.isa b/src/arch/arm/isa/bitfields.isa
index c9696a115db9106189585c7b5ac7b1623d8d452b..1dcbddec3c50b6d9518c640b33116901c11bee3e 100644 (file)
--- a/src/arch/arm/isa/bitfields.isa
+++ b/src/arch/arm/isa/bitfields.isa
@@ -143,6 +143,7 @@ def bitfield HTOPCODE_8     htopcode8;
 def bitfield HTOPCODE_8_7   htopcode8_7;
 def bitfield HTOPCODE_8_6   htopcode8_6;
 def bitfield HTOPCODE_8_5   htopcode8_5;
+def bitfield HTOPCODE_7     htopcode7;
 def bitfield HTOPCODE_6_5   htopcode6_5;
 def bitfield HTOPCODE_5_4   htopcode5_4;
 def bitfield HTOPCODE_4     htopcode4;
@@ -151,6 +152,8 @@ def bitfield HTRN           htrn;
 def bitfield HTS            hts;
 
 def bitfield LTOPCODE_15    ltopcode15;
+def bitfield LTOPCODE_11_8  ltopcode11_8;
+def bitfield LTOPCODE_7_6   ltopcode7_6;
 def bitfield LTOPCODE_7_4   ltopcode7_4;
 def bitfield LTOPCODE_4     ltopcode4;
 

diff --git a/src/arch/arm/isa/thumbdecode.isa b/src/arch/arm/isa/thumbdecode.isa
index 682a9824921edd9ea15dfa4adf5717f68a60917b..3d8e56a48dc34fe0236eff6b76bf10039682b30a 100644 (file)
--- a/src/arch/arm/isa/thumbdecode.isa
+++ b/src/arch/arm/isa/thumbdecode.isa
@@ -394,7 +394,22 @@
                 0x1: decode HTOPCODE_6_5 {
                     0x0: WarnUnimpl::Load_byte_memory_hints();
                     0x1: WarnUnimpl::Load_halfword_memory_hints();
-                    0x2: WarnUnimpl::Load_word();
+                    0x2: decode HTOPCODE_8 {
+                        0x0: decode HTRN {
+                            0xf: WarnUnimpl::ldr(); // literal A8-122
+                            default: decode HTOPCODE_7 {
+                                0x0: decode LTOPCODE_11_8 {
+                                    0x0: decode LTOPCODE_7_6 {
+                                        0x0: WarnUnimpl::ldr(); // register A8-122
+                                    }
+                                    0x9, 0xb, 0xc, 0xd, 0xf:
+                                        WarnUnimpl::ldr(); // immediate thumb A8-118
+                                    0xe: WarnUnimpl::ldrt(); // A8-176
+                                }
+                                0x1: WarnUnimpl::ldr(); // immediate thumb A8-118
+                            }
+                        }
+                    }
                     0x3: WarnUnimpl::undefined();
                 }
             }

diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index c3dcfe28add701878cceebbe103c5912698a2ab5..23152d3cf1bacf51609dc2b63c03935514fe8fbe 100644 (file)
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -155,6 +155,7 @@ namespace ArmISA
         Bitfield<24, 23> htopcode8_7;
         Bitfield<24, 22> htopcode8_6;
         Bitfield<24, 21> htopcode8_5;
+        Bitfield<23>     htopcode7;
         Bitfield<22, 21> htopcode6_5;
         Bitfield<21, 20> htopcode5_4;
         Bitfield<20>     htopcode4;
@@ -163,6 +164,8 @@ namespace ArmISA
         Bitfield<20>     hts;
 
         Bitfield<15>     ltopcode15;
+        Bitfield<11, 8>  ltopcode11_8;
+        Bitfield<7,  6>  ltopcode7_6;
         Bitfield<7,  4>  ltopcode7_4;
         Bitfield<4>      ltopcode4;