interconnect/axi: remove bus_name on connect_to_pads

diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py
index 58755b92b6a436fb02d4604e4ab41ff83d833950..905ef58675613062bebee6547c183d7243c3e7a8 100644 (file)
--- a/litex/soc/interconnect/axi.py
+++ b/litex/soc/interconnect/axi.py
@@ -110,7 +110,7 @@ class AXILiteInterface(Record):
         ios = [(bus_name , 0) + tuple(subsignals)]
         return ios
 
-    def connect_to_pads(self, pads, bus_name, mode="master"):
+    def connect_to_pads(self, pads, mode="master"):
         assert mode in ["slave", "master"]
         r = []
         def swap_mode(mode): return "master" if mode == "slave" else "slave"

diff --git a/litex/tools/litex_gen.py b/litex/tools/litex_gen.py
index 28fc95317cade05fb65a30be0154d4c7ad01f9df..465be327f7f1cda55bdba53822c03fa4d4608760 100755 (executable)
--- a/litex/tools/litex_gen.py
+++ b/litex/tools/litex_gen.py
@@ -102,7 +102,7 @@ class LiteXCore(SoCMini):
             self.bus.add_master(master=wb_bus)
             platform.add_extension(axi_bus.get_ios("axi"))
             axi_pads = platform.request("axi")
-            self.comb += axi_bus.connect_to_pads(axi_pads, "axi", mode="slave")
+            self.comb += axi_bus.connect_to_pads(axi_pads, mode="slave")
 
         # IRQs
         for name, loc in sorted(self.irq.locs.items()):