techlibs/common: more robustness when *_WIDTH = 0

diff --git a/techlibs/common/cmp2lcu.v b/techlibs/common/cmp2lcu.v
index b6f4aeed6f455891ab47e1a84918d2fc6d0bdff2..e42f346d142aaf07585f6f2cc3e4f2b27e81c361 100644 (file)
--- a/techlibs/common/cmp2lcu.v
+++ b/techlibs/common/cmp2lcu.v
@@ -108,8 +108,12 @@ generate
                 // Generate if any comparisons call for it
                 wire [LCU_WIDTH-1:0] G_ = {G[LCU_WIDTH-1:1], G[0] | GG};
             end
-            $__CMP2LCU #(.AB_WIDTH(AB_WIDTH-1), .AB_SIGNED(1'b0), .LCU_WIDTH(LCU_WIDTH), .BUDGET(BUDGET-COST), .CI(CI))
-                _TECHMAP_REPLACE_ (.A(A[AB_WIDTH-2:0]), .B(B[AB_WIDTH-2:0]), .P(P_), .G(G_), .Y(Y));
+            if (AB_WIDTH == 1)
+               $__CMP2LCU #(.AB_WIDTH(AB_WIDTH-1), .AB_SIGNED(1'b0), .LCU_WIDTH(LCU_WIDTH), .BUDGET(BUDGET-COST), .CI(CI))
+                    _TECHMAP_REPLACE_ (.A(), .B(), .P(P_), .G(G_), .Y(Y));
+            else
+               $__CMP2LCU #(.AB_WIDTH(AB_WIDTH-1), .AB_SIGNED(1'b0), .LCU_WIDTH(LCU_WIDTH), .BUDGET(BUDGET-COST), .CI(CI))
+                    _TECHMAP_REPLACE_ (.A(A[AB_WIDTH-2:0]), .B(B[AB_WIDTH-2:0]), .P(P_), .G(G_), .Y(Y));
         end
     end
 endgenerate

diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index ecf4d5dc5466b87c031ef52f7feb014da09ea43e..225cff449d6b905d08d9c52ef846ec0856c7eef4 100644 (file)
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -285,13 +285,32 @@ module _90_alu (A, B, CI, BI, X, Y, CO);
        input CI, BI;
        output [Y_WIDTH-1:0] CO;
 
-       wire [Y_WIDTH-1:0] A_buf, B_buf;
-       \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
-       \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
-
-       wire [Y_WIDTH-1:0] AA = A_buf;
+       wire [Y_WIDTH-1:0] AA, BB;
        wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
 
+       if (A_WIDTH == 0) begin
+               wire [Y_WIDTH-1:0] B_buf;
+               \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+               assign AA = {Y_WIDTH{1'b0}};
+               assign BB = BI ? ~B_buf : B_buf;
+       end
+       else if (B_WIDTH == 0) begin
+               wire [Y_WIDTH-1:0] A_buf;
+               \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+
+               assign AA = A_buf;
+               assign BB = {Y_WIDTH{BI ? 1'b0 : 1'b1}};
+       end
+       else begin
+               wire [Y_WIDTH-1:0] A_buf, B_buf;
+               \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+               \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+               assign AA = A_buf;
+               assign BB = BI ? ~B_buf : B_buf;
+       end
+
        \$lcu #(.WIDTH(Y_WIDTH)) lcu (.P(X), .G(AA & BB), .CI(CI), .CO(CO));
 
        assign X = AA ^ BB;

diff --git a/tests/verilog/upto.ys b/tests/verilog/upto.ys
index d87f4424ea3a77d712ed64398d8af2942753c33b..2f3394761cc54e1ba3d4aa8091a83cbb21da1836 100644 (file)
--- a/tests/verilog/upto.ys
+++ b/tests/verilog/upto.ys
@@ -2,4 +2,3 @@ read_verilog <<EOT
 module top(input [-128:-65] a);
 endmodule
 EOT
-dump