soc/itnegration: update litedram

diff --git a/litex/soc/integration/builder.py b/litex/soc/integration/builder.py
index 28fc145aab562de310c6d3a6b96db42a0d990d49..b656f99836e4a7b56e3bacf4a8d6f8a4f2cacb08 100644 (file)
--- a/litex/soc/integration/builder.py
+++ b/litex/soc/integration/builder.py
@@ -16,7 +16,7 @@ import shutil
 from litex.build.tools import write_to_file
 from litex.soc.integration import cpu_interface, soc_core, soc_sdram
 
-from litedram import sdram_init
+from litedram.init import get_sdram_phy_c_header
 
 __all__ = ["soc_software_packages", "soc_directory",
            "Builder", "builder_args", "builder_argdict"]
@@ -125,7 +125,7 @@ class Builder:
             if hasattr(self.soc, "sdram"):
                 write_to_file(
                     os.path.join(generated_dir, "sdram_phy.h"),
-                    sdram_init.get_sdram_phy_c_header(
+                    get_sdram_phy_c_header(
                         self.soc.sdram.controller.settings.phy,
                         self.soc.sdram.controller.settings.timing))
 

diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py
index 1706ae41f414e9d89d60fe195a17397d0703eac8..c148fac874f4e4db0189a9adbef64c13475f578e 100644 (file)
--- a/litex/soc/integration/soc_sdram.py
+++ b/litex/soc/integration/soc_sdram.py
@@ -20,7 +20,7 @@ __all__ = ["SoCSDRAM", "soc_sdram_args", "soc_sdram_argdict"]
 
 
 class ControllerInjector(Module, AutoCSR):
-    def __init__(self, phy, geom_settings, timing_settings, **kwargs):
+    def __init__(self, phy, geom_settings, timing_settings, clk_freq, **kwargs):
         self.submodules.dfii = dfii.DFIInjector(
             geom_settings.addressbits,
             geom_settings.bankbits,
@@ -30,7 +30,8 @@ class ControllerInjector(Module, AutoCSR):
         self.comb += self.dfii.master.connect(phy.dfi)
 
         self.submodules.controller = controller = core.LiteDRAMController(
-            phy.settings, geom_settings, timing_settings, **kwargs)
+            phy.settings, geom_settings, timing_settings,
+            clk_freq, **kwargs)
         self.comb += controller.dfi.connect(self.dfii.slave)
 
         self.submodules.crossbar = core.LiteDRAMCrossbar(controller.interface)
@@ -64,7 +65,7 @@ class SoCSDRAM(SoCCore):
         self._sdram_phy.append(phy)  # encapsulate in list to prevent CSR scanning
 
         self.submodules.sdram = ControllerInjector(
-            phy, geom_settings, timing_settings, **kwargs)
+            phy, geom_settings, timing_settings, self.clk_freq, **kwargs)
 
         main_ram_size = 2**(geom_settings.bankbits +
                             geom_settings.rowbits +