mention aliases

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 254a66010d4757e0c51d50f255b1a27d1bcfe408..b222975dd149d1f4931b201cae7ca46382d55bae 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -136,6 +136,7 @@ such large numbers of registers, even for Multi-Issue microarchitectures.
 * To hold all Vector Context, five SPRs are needed for userspace.
   If Supervisor and Hypervisor mode are to
   also support Simple-V they will correspondingly need five SPRs each.
+  (Some 32/32-to-64 aliases are advantageous but not critical).
 * Five 6-bit XO (A-Form) "Management" instructions are needed.  These are
   Scalar 32-bit instructions and *may* be 64-bit-extended in future
   (safely within the SVP64 space: no need for an EXT001 encoding).