+2013-07-18 Sofiane Naci <sofiane.naci@arm.com>
+
+ * config/arm/arm.md (attribute "type"): Rename "simple_alu_imm" to
+ "arlo_imm". Rename "alu_reg" to "arlo_reg". Rename "simple_alu_shift" to
+ "extend". Split "alu_shift" into "shift" and "arlo_shift". Split
+ "alu_shift_reg" into "shift_reg" and "arlo_shift_reg". List types
+ in alphabetical order.
+ (attribute "core_cycles"): Update for attribute changes.
+ (arm_addsi3): Likewise.
+ (addsi3_compare0): Likewise.
+ (addsi3_compare0_scratch): Likewise.
+ (addsi3_compare_op1): Likewise.
+ (addsi3_compare_op2): Likewise.
+ (compare_addsi2_op0): Likewise.
+ (compare_addsi2_op1): Likewise.
+ (addsi3_carryin_shift_<optab>): Likewise.
+ (subsi3_carryin_shift): Likewise.
+ (rsbsi3_carryin_shift): Likewise.
+ (arm_subsi3_insn): Likewise.
+ (subsi3_compare0): Likewise.
+ (subsi3_compare): Likewise.
+ (arm_andsi3_insn): Likewise.
+ (thumb1_andsi3_insn): Likewise.
+ (andsi3_compare0): Likewise.
+ (andsi3_compare0_scratch): Likewise.
+ (zeroextractsi_compare0_scratch
+ (andsi_not_shiftsi_si): Likewise.
+ (iorsi3_insn): Likewise.
+ (iorsi3_compare0): Likewise.
+ (iorsi3_compare0_scratch): Likewise.
+ (arm_xorsi3): Likewise.
+ (thumb1_xorsi3_insn): Likewise.
+ (xorsi3_compare0): Likewise.
+ (xorsi3_compare0_scratch): Likewise.
+ (satsi_<SAT:code>_shift): Likewise.
+ (rrx): Likewise.
+ (arm_shiftsi3): Likewise.
+ (shiftsi3_compare0): Likewise.
+ (not_shiftsi): Likewise.
+ (not_shiftsi_compare0): Likewise.
+ (not_shiftsi_compare0_scratch): Likewise.
+ (arm_one_cmplsi2): Likewise.
+ (thumb_one_complsi2): Likewise.
+ (notsi_compare0): Likewise.
+ (notsi_compare0_scratch): Likewise.
+ (thumb1_zero_extendhisi2): Likewise.
+ (arm_zero_extendhisi2): Likewise.
+ (arm_zero_extendhisi2_v6): Likewise.
+ (arm_zero_extendhisi2addsi): Likewise.
+ (thumb1_zero_extendqisi2): Likewise.
+ (thumb1_zero_extendqisi2_v6): Likewise.
+ (arm_zero_extendqisi2): Likewise.
+ (arm_zero_extendqisi2_v6): Likewise.
+ (arm_zero_extendqisi2addsi): Likewise.
+ (thumb1_extendhisi2): Likewise.
+ (arm_extendhisi2): Likewise.
+ (arm_extendhisi2_v6): Likewise.
+ (arm_extendqisi): Likewise.
+ (arm_extendqisi_v6): Likewise.
+ (arm_extendqisi2addsi): Likewise.
+ (thumb1_extendqisi2): Likewise.
+ (thumb1_movdi_insn): Likewise.
+ (arm_movsi_insn): Likewise.
+ (movsi_compare0): Likewise.
+ (movhi_insn_arch4): Likewise.
+ (movhi_bytes): Likewise.
+ (arm_movqi_insn): Likewise.
+ (thumb1_movqi_insn): Likewise.
+ (arm32_movhf): Likewise.
+ (thumb1_movhf): Likewise.
+ (arm_movsf_soft_insn): Likewise.
+ (thumb1_movsf_insn): Likewise.
+ (movdf_soft_insn): Likewise.
+ (thumb_movdf_insn): Likewise.
+ (arm_cmpsi_insn): Likewise.
+ (cmpsi_shiftsi): Likewise.
+ (cmpsi_shiftsi_swp): Likewise.
+ (arm_cmpsi_negshiftsi_si): Likewise.
+ (movsicc_insn): Likewise.
+ (movsfcc_soft_insn): Likewise.
+ (arith_shiftsi): Likewise.
+ (arith_shiftsi_compare0
+ (arith_shiftsi_compare0_scratch
+ (sub_shiftsi): Likewise.
+ (sub_shiftsi_compare0
+ (sub_shiftsi_compare0_scratch
+ (and_scc): Likewise.
+ (cond_move): Likewise.
+ (if_plus_move): Likewise.
+ (if_move_plus): Likewise.
+ (if_move_not): Likewise.
+ (if_not_move): Likewise.
+ (if_shift_move): Likewise.
+ (if_move_shift): Likewise.
+ (if_shift_shift): Likewise.
+ (if_not_arith): Likewise.
+ (if_arith_not): Likewise.
+ (cond_move_not): Likewise.
+ (thumb1_ashlsi3): Set type attribute.
+ (thumb1_ashrsi3): Likewise.
+ (thumb1_lshrsi3): Likewise.
+ (thumb1_rotrsi3): Likewise.
+ (shiftsi3_compare0_scratch): Likewise.
+ * config/arm/neon.md (neon_mov<mode>): Update for attribute changes.
+ (neon_mov<mode>): Likewise.
+ * config/arm/thumb2.md (thumb_andsi_not_shiftsi_si): Update for attribute
+ changes.
+ (thumb2_movsi_insn): Likewise.
+ (thumb2_cmpsi_neg_shiftsi): Likewise.
+ (thumb2_extendqisi_v6): Likewise.
+ (thumb2_zero_extendhisi2_v6): Likewise.
+ (thumb2_zero_extendqisi2_v6): Likewise.
+ (thumb2_shiftsi3_short): Likewise.
+ (thumb2_addsi3_compare0_scratch): Likewise.
+ (orsi_not_shiftsi_si): Likewise.
+ * config/arm/vfp.md (arm_movsi_vfp): Update for attribute changes.
+ * config/arm/arm-fixed.md (arm_ssatsihi_shift): Update for attribute
+ changes.
+ * config/arm/arm1020e.md (1020alu_op): Update for attribute changes.
+ (1020alu_shift_op): Likewise.
+ (1020alu_shift_reg_op): Likewise.
+ * config/arm/arm1026ejs.md (alu_op): Update for attribute changes.
+ (alu_shift_op): Likewise.
+ (alu_shift_reg_op): Likewise.
+ * config/arm/arm1136jfs.md (11_alu_op): Update for attribute changes.
+ (11_alu_shift_op): Likewise.
+ (11_alu_shift_reg_op): Likewise.
+ * config/arm/arm926ejs.md (9_alu_op): Update for attribute changes.
+ (9_alu_shift_reg_op): Likewise.
+ * config/arm/cortex-a15.md (cortex_a15_alu): Update for attribute changes.
+ (cortex_a15_alu_shift): Likewise.
+ (cortex_a15_alu_shift_reg): Likewise.
+ * config/arm/cortex-a5.md (cortex_a5_alu): Update for attribute changes.
+ (cortex_a5_alu_shift): Likewise.
+ * config/arm/cortex-a53.md (cortex_a53_alu) : Update for attribute
+ changes.
+ (cortex_a53_alu_shift): Likewise.
+ * config/arm/cortex-a7.md (cortex_a7_alu_imm): Update for attribute
+ changes.
+ (cortex_a7_alu_reg): Likewise.
+ (cortex_a7_alu_shift): Likewise.
+ * config/arm/cortex-a8.md (cortex_a8_alu): Update for attribute changes.
+ (cortex_a8_alu_shift): Likewise.
+ (cortex_a8_alu_shift_reg): Likewise.
+ (cortex_a8_mov): Likewise.
+ * config/arm/cortex-a9.md (cortex_a9_dp): Update for attribute changes.
+ (cortex_a9_dp_shift): Likewise.
+ * config/arm/cortex-m4.md (cortex_m4_alu): Update for attribute changes.
+ * config/arm/cortex-r4.md (cortex_r4_alu): Update for attribute changes.
+ (cortex_r4_mov): Likewise.
+ (cortex_r4_alu_shift): Likewise.
+ (cortex_r4_alu_shift_reg): Likewise.
+ * config/arm/fa526.md (526_alu_op): Update for attribute changes.
+ (526_alu_shift_op): Likewise.
+ * config/arm/fa606te.md (606te_alu_op): Update for attribute changes.
+ * config/arm/fa626te.md (626te_alu_op): Update for attribute changes.
+ (626te_alu_shift_op): Likewise.
+ * config/arm/fa726te.md (726te_shift_op): Update for attribute changes.
+ (726te_alu_op): Likewise.
+ (726te_alu_shift_op): Likewise.
+ (726te_alu_shift_reg_op): Likewise.
+ * config/arm/fmp626.md (mp626_alu_op): Update for attribute changes.
+ (mp626_alu_shift_op): Likewise.
+ * config/arm/marvell-pj4.md (pj4_alu_e1): Update for attribute changes.
+ (pj4_alu_e1_conds): Likewise.
+ (pj4_alu): Likewise.
+ (pj4_alu_conds): Likewise.
+ (pj4_shift): Likewise.
+ (pj4_shift_conds): Likewise.
+ (pj4_alu_shift): Likewise.
+ (pj4_alu_shift_conds): Likewise.
+ * config/arm/arm.c (xscale_sched_adjust_cost): Update for attribute changes.
+ (cortexa7_older_only): Likewise.
+ (cortexa7_younger): Likewise.
+
2013-07-18 David Malcolm <dmalcolm@redhat.com>
* ipa-pure-const.c (generate_summary): Rename to...
(set_attr "predicable_short_it" "no")
(set_attr "insn" "sat")
(set_attr "shift" "1")
- (set_attr "type" "alu_shift")])
+ (set_attr "type" "arlo_shift")])
(define_insn "arm_usatsihi"
[(set (match_operand:HI 0 "s_register_operand" "=r")
instruction we depend on is another ALU instruction, then we may
have to account for an additional stall. */
if (shift_opnum != 0
- && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG))
+ && (attr_type == TYPE_ARLO_SHIFT || attr_type == TYPE_ARLO_SHIFT_REG))
{
rtx shifted_operand;
int opno;
switch (get_attr_type (insn))
{
- case TYPE_ALU_REG:
+ case TYPE_ARLO_REG:
+ case TYPE_SHIFT:
+ case TYPE_SHIFT_REG:
case TYPE_LOAD_BYTE:
case TYPE_LOAD1:
case TYPE_STORE1:
switch (get_attr_type (insn))
{
- case TYPE_SIMPLE_ALU_IMM:
- case TYPE_SIMPLE_ALU_SHIFT:
+ case TYPE_ARLO_IMM:
+ case TYPE_EXTEND:
case TYPE_BRANCH:
case TYPE_CALL:
return true;
;
; Instruction classification:
;
-; alu_reg any alu instruction that doesn't hit memory or fp
-; regs or have a shifted source operand and does not have
-; an immediate operand. This is also the default.
-; alu_shift any data instruction that doesn't hit memory or fp.
-; regs, but has a source operand shifted by a constant.
-; alu_shift_reg any data instruction that doesn't hit memory or fp.
+; arlo_imm any arithmetic or logical instruction that doesn't have
+; a shifted operand and has an immediate operand. This
+; excludes MOV, MVN and RSB(S) immediate.
+; arlo_reg any arithmetic or logical instruction that doesn't have
+; a shifted or an immediate operand. This excludes
+; MOV and MVN but includes MOVT. This is also the default.
+; arlo_shift any arithmetic or logical instruction that has a source
+; operand shifted by a constant. This excludes
+; simple shifts.
+; arlo_shift_reg as arlo_shift, with the shift amount specified in a
+; register.
; block blockage insn, this blocks all functional units.
; branch branch.
; call subroutine call.
+; extend extend instruction (SXTB, SXTH, UXTB, UXTH).
; f_2_r transfer from float to core (no memory needed).
; f_cvt conversion between float and integral.
; f_flag transfer of co-processor flags to the CPSR.
; muls integer multiply, flag setting.
; r_2_f transfer from core to float.
; sdiv signed division.
-; simple_alu_imm simple alu instruction that doesn't hit memory or fp
-; regs or have a shifted source operand and has an
-; immediate operand. This currently only tracks very basic
-; immediate alu operations.
-; simple_alu_shift simple alu instruction with a shifted source operand.
+; shift simple shift operation (LSL, LSR, ASR, ROR) with an
+; immediate.
+; shift_reg simple shift by a register.
; smlad signed multiply accumulate dual.
; smladx signed multiply accumulate dual reverse.
; smlal signed multiply accumulate long.
; wmmx_wxor
(define_attr "type"
- "simple_alu_imm,\
- alu_reg,\
- simple_alu_shift,\
- alu_shift,\
- alu_shift_reg,\
+ "arlo_imm,\
+ arlo_reg,\
+ arlo_shift,\
+ arlo_shift_reg,\
block,\
- float,\
- fdivd,\
- fdivs,\
- fmuls,\
- fmuld,\
- fmacs,\
- fmacd,\
- ffmas,\
- ffmad,\
- f_rints,\
- f_rintd,\
- f_minmaxs,\
- f_minmaxd,\
- f_flag,\
- f_loads,\
- f_loadd,\
- f_stores,\
- f_stored,\
+ branch,\
+ call,\
+ complex,\
+ extend,\
f_2_r,\
- r_2_f,\
f_cvt,\
- f_sels,\
+ f_flag,\
+ f_loadd,\
+ f_loads,\
+ f_minmaxd,\
+ f_minmaxs,\
+ f_rintd,\
+ f_rints,\
f_seld,\
- branch,\
- call,\
+ f_sels,\
+ f_stored,\
+ f_stores,\
+ faddd,\
+ fadds,\
+ fcmpd,\
+ fcmps,\
+ fconstd,\
+ fconsts,\
+ fcpys,\
+ fdivd,\
+ fdivs,\
+ ffarithd,\
+ ffariths,\
+ ffmad,\
+ ffmas,\
+ float,\
+ fmacd,\
+ fmacs,\
+ fmuld,\
+ fmuls,\
load_byte,\
load1,\
load2,\
load3,\
load4,\
- store1,\
- store2,\
- store3,\
- store4,\
- fconsts,\
- fconstd,\
- fadds,\
- faddd,\
- ffariths,\
- ffarithd,\
- fcmps,\
- fcmpd,\
- fcpys,\
- smulxy,\
- smlaxy,\
- smlalxy,\
- smulwy,\
- smlawx,\
- mul,\
- muls,\
mla,\
mlas,\
- umull,\
- umulls,\
- umlal,\
- umlals,\
- smull,\
- smulls,\
+ mul,\
+ muls,\
+ r_2_f,\
+ sdiv,\
+ shift,\
+ shift_reg,\
+ smlad,\
+ smladx,\
smlal,\
+ smlald,\
smlals,\
+ smlalxy,\
+ smlawx,\
smlawy,\
- smuad,\
- smuadx,\
- smlad,\
- smladx,\
- smusd,\
- smusdx,\
+ smlaxy,\
smlsd,\
smlsdx,\
+ smlsld,\
+ smmla,\
smmul,\
smmulr,\
- smmla,\
- umaal,\
- smlald,\
- smlsld,\
- sdiv,\
+ smuad,\
+ smuadx,\
+ smull,\
+ smulls,\
+ smulwy,\
+ smulxy,\
+ smusd,\
+ smusdx,\
+ store1,\
+ store2,\
+ store3,\
+ store4,\
udiv,\
+ umaal,\
+ umlal,\
+ umlals,\
+ umull,\
+ umulls,\
wmmx_tandc,\
wmmx_tbcst,\
wmmx_textrc,\
wmmx_wunpckih,\
wmmx_wunpckil,\
wmmx_wxor"
- (const_string "alu_reg"))
+ (const_string "arlo_reg"))
; Is this an (integer side) multiply with a 32-bit (or smaller) result?
(define_attr "mul32" "no,yes"
; than one on the main cpu execution unit.
(define_attr "core_cycles" "single,multi"
(if_then_else (eq_attr "type"
- "simple_alu_imm, alu_reg,\
- simple_alu_shift, alu_shift, float, fdivd, fdivs,\
+ "arlo_imm, arlo_reg,\
+ extend, shift, arlo_shift, float, fdivd, fdivs,\
wmmx_wor, wmmx_wxor, wmmx_wand, wmmx_wandn, wmmx_wmov, wmmx_tmcrr,\
wmmx_tmrrc, wmmx_wldr, wmmx_wstr, wmmx_tmcr, wmmx_tmrc, wmmx_wadd,\
wmmx_wsub, wmmx_wmul, wmmx_wmac, wmmx_wavg2, wmmx_tinsr, wmmx_textrm,\
(set_attr "predicable" "yes")
(set_attr "arch" "t2,*,*,*,t2,t2,*,*,a,t2,t2,*")
(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
- (const_string "simple_alu_imm")
- (const_string "alu_reg")))
+ (const_string "arlo_imm")
+ (const_string "arlo_reg")))
]
)
sub%.\\t%0, %1, #%n2
add%.\\t%0, %1, %2"
[(set_attr "conds" "set")
- (set_attr "type" "simple_alu_imm, simple_alu_imm, *")]
+ (set_attr "type" "arlo_imm,arlo_imm,*")]
)
(define_insn "*addsi3_compare0_scratch"
cmn%?\\t%0, %1"
[(set_attr "conds" "set")
(set_attr "predicable" "yes")
- (set_attr "type" "simple_alu_imm, simple_alu_imm, *")
+ (set_attr "type" "arlo_imm,arlo_imm,*")
]
)
sub%.\\t%0, %1, #%n2
add%.\\t%0, %1, %2"
[(set_attr "conds" "set")
- (set_attr "type" "simple_alu_imm,simple_alu_imm,*")]
+ (set_attr "type" "arlo_imm,arlo_imm,*")]
)
(define_insn "*addsi3_compare_op2"
add%.\\t%0, %1, %2
sub%.\\t%0, %1, #%n2"
[(set_attr "conds" "set")
- (set_attr "type" "simple_alu_imm,simple_alu_imm,*")]
+ (set_attr "type" "arlo_imm,arlo_imm,*")]
)
(define_insn "*compare_addsi2_op0"
cmn%?\\t%0, %1"
[(set_attr "conds" "set")
(set_attr "predicable" "yes")
- (set_attr "type" "simple_alu_imm,simple_alu_imm,*")]
+ (set_attr "type" "arlo_imm,arlo_imm,*")]
)
(define_insn "*compare_addsi2_op1"
cmn%?\\t%0, %1"
[(set_attr "conds" "set")
(set_attr "predicable" "yes")
- (set_attr "type" "simple_alu_imm,simple_alu_imm,*")]
+ (set_attr "type" "arlo_imm,arlo_imm,*")]
)
(define_insn "*addsi3_carryin_<optab>"
[(set_attr "conds" "use")
(set_attr "predicable" "yes")
(set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
- (const_string "alu_shift")
- (const_string "alu_shift_reg")))]
+ (const_string "arlo_shift")
+ (const_string "arlo_shift_reg")))]
)
(define_insn "*addsi3_carryin_clobercc_<optab>"
[(set_attr "conds" "use")
(set_attr "predicable" "yes")
(set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
- (const_string "alu_shift")
- (const_string "alu_shift_reg")))]
+ (const_string "arlo_shift")
+ (const_string "arlo_shift_reg")))]
)
(define_insn "*rsbsi3_carryin_shift"
[(set_attr "conds" "use")
(set_attr "predicable" "yes")
(set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
- (const_string "alu_shift")
- (const_string "alu_shift_reg")))]
+ (const_string "arlo_shift")
+ (const_string "arlo_shift_reg")))]
)
; transform ((x << y) - 1) to ~(~(x-1) << y) Where X is a constant.
"
[(set_attr "length" "4,4,4,4,16")
(set_attr "predicable" "yes")
- (set_attr "type" "*,simple_alu_imm,*,*,*")]
+ (set_attr "type" "*,arlo_imm,*,*,*")]
)
(define_peephole2
sub%.\\t%0, %1, %2
rsb%.\\t%0, %2, %1"
[(set_attr "conds" "set")
- (set_attr "type" "simple_alu_imm,*,*")]
+ (set_attr "type" "arlo_imm,*,*")]
)
(define_insn "subsi3_compare"
sub%.\\t%0, %1, %2
rsb%.\\t%0, %2, %1"
[(set_attr "conds" "set")
- (set_attr "type" "simple_alu_imm,*,*")]
+ (set_attr "type" "arlo_imm,*,*")]
)
(define_expand "subsf3"
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no,yes,no,no,no")
(set_attr "type"
- "simple_alu_imm,simple_alu_imm,*,*,simple_alu_imm")]
+ "arlo_imm,arlo_imm,*,*,arlo_imm")]
)
(define_insn "*thumb1_andsi3_insn"
"TARGET_THUMB1"
"and\\t%0, %2"
[(set_attr "length" "2")
- (set_attr "type" "simple_alu_imm")
+ (set_attr "type" "arlo_imm")
(set_attr "conds" "set")])
(define_insn "*andsi3_compare0"
bic%.\\t%0, %1, #%B2
and%.\\t%0, %1, %2"
[(set_attr "conds" "set")
- (set_attr "type" "simple_alu_imm,simple_alu_imm,*")]
+ (set_attr "type" "arlo_imm,arlo_imm,*")]
)
(define_insn "*andsi3_compare0_scratch"
bic%.\\t%2, %0, #%B1
tst%?\\t%0, %1"
[(set_attr "conds" "set")
- (set_attr "type" "simple_alu_imm,simple_alu_imm,*")]
+ (set_attr "type" "arlo_imm,arlo_imm,*")]
)
(define_insn "*zeroextractsi_compare0_scratch"
[(set_attr "conds" "set")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
- (set_attr "type" "simple_alu_imm")]
+ (set_attr "type" "arlo_imm")]
)
(define_insn_and_split "*ne_zeroextractsi"
[(set_attr "predicable" "yes")
(set_attr "shift" "2")
(set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
- (const_string "alu_shift")
- (const_string "alu_shift_reg")))]
+ (const_string "arlo_shift")
+ (const_string "arlo_shift_reg")))]
)
(define_insn "*andsi_notsi_si_compare0"
(set_attr "arch" "32,t2,t2,32,32")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no,yes,no,no,no")
- (set_attr "type" "simple_alu_imm,*,simple_alu_imm,*,*")]
+ (set_attr "type" "arlo_imm,*,arlo_imm,*,*")]
)
(define_insn "*thumb1_iorsi3_insn"
"TARGET_32BIT"
"orr%.\\t%0, %1, %2"
[(set_attr "conds" "set")
- (set_attr "type" "simple_alu_imm,*")]
+ (set_attr "type" "arlo_imm,*")]
)
(define_insn "*iorsi3_compare0_scratch"
"TARGET_32BIT"
"orr%.\\t%0, %1, %2"
[(set_attr "conds" "set")
- (set_attr "type" "simple_alu_imm, *")]
+ (set_attr "type" "arlo_imm,*")]
)
(define_expand "xordi3"
[(set_attr "length" "4,4,4,16")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no,yes,no,no")
- (set_attr "type" "simple_alu_imm,*,*,*")]
+ (set_attr "type" "arlo_imm,*,*,*")]
)
(define_insn "*thumb1_xorsi3_insn"
"eor\\t%0, %2"
[(set_attr "length" "2")
(set_attr "conds" "set")
- (set_attr "type" "simple_alu_imm")]
+ (set_attr "type" "arlo_imm")]
)
(define_insn "*xorsi3_compare0"
"TARGET_32BIT"
"eor%.\\t%0, %1, %2"
[(set_attr "conds" "set")
- (set_attr "type" "simple_alu_imm,*")]
+ (set_attr "type" "arlo_imm,*")]
)
(define_insn "*xorsi3_compare0_scratch"
"TARGET_32BIT"
"teq%?\\t%0, %1"
[(set_attr "conds" "set")
- (set_attr "type" "simple_alu_imm, *")]
+ (set_attr "type" "arlo_imm,*")]
)
; By splitting (IOR (AND (NOT A) (NOT B)) C) as D = AND (IOR A B) (NOT C),
[(set_attr "predicable" "yes")
(set_attr "insn" "sat")
(set_attr "shift" "3")
- (set_attr "type" "alu_shift")])
+ (set_attr "type" "arlo_shift")])
\f
;; Shift and rotation insns
"TARGET_THUMB1"
"lsl\\t%0, %1, %2"
[(set_attr "length" "2")
+ (set_attr "type" "shift,shift_reg")
(set_attr "conds" "set")])
(define_expand "ashrdi3"
"mov\\t%0, %1, rrx"
[(set_attr "conds" "use")
(set_attr "insn" "mov")
- (set_attr "type" "alu_shift")]
+ (set_attr "type" "arlo_shift")]
)
(define_expand "ashrsi3"
"TARGET_THUMB1"
"asr\\t%0, %1, %2"
[(set_attr "length" "2")
+ (set_attr "type" "shift,shift_reg")
(set_attr "conds" "set")])
(define_expand "lshrdi3"
"TARGET_THUMB1"
"lsr\\t%0, %1, %2"
[(set_attr "length" "2")
+ (set_attr "type" "shift,shift_reg")
(set_attr "conds" "set")])
(define_expand "rotlsi3"
(match_operand:SI 2 "register_operand" "l")))]
"TARGET_THUMB1"
"ror\\t%0, %0, %2"
- [(set_attr "length" "2")]
+ [(set_attr "type" "shift_reg")
+ (set_attr "length" "2")]
)
(define_insn "*arm_shiftsi3"
- [(set (match_operand:SI 0 "s_register_operand" "=r")
+ [(set (match_operand:SI 0 "s_register_operand" "=r,r")
(match_operator:SI 3 "shift_operator"
- [(match_operand:SI 1 "s_register_operand" "r")
- (match_operand:SI 2 "reg_or_int_operand" "rM")]))]
+ [(match_operand:SI 1 "s_register_operand" "r,r")
+ (match_operand:SI 2 "reg_or_int_operand" "M,r")]))]
"TARGET_32BIT"
"* return arm_output_shift(operands, 0);"
[(set_attr "predicable" "yes")
(set_attr "shift" "1")
- (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
- (const_string "alu_shift")
- (const_string "alu_shift_reg")))]
+ (set_attr "type" "arlo_shift,arlo_shift_reg")]
)
(define_insn "*shiftsi3_compare"
[(set (reg:CC CC_REGNUM)
(compare:CC (match_operator:SI 3 "shift_operator"
- [(match_operand:SI 1 "s_register_operand" "r")
- (match_operand:SI 2 "arm_rhs_operand" "rM")])
+ [(match_operand:SI 1 "s_register_operand" "r,r")
+ (match_operand:SI 2 "arm_rhs_operand" "M,r")])
(const_int 0)))
- (set (match_operand:SI 0 "s_register_operand" "=r")
+ (set (match_operand:SI 0 "s_register_operand" "=r,r")
(match_op_dup 3 [(match_dup 1) (match_dup 2)]))]
"TARGET_32BIT"
"* return arm_output_shift(operands, 1);"
[(set_attr "conds" "set")
(set_attr "shift" "1")
- (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
- (const_string "alu_shift")
- (const_string "alu_shift_reg")))]
+ (set_attr "type" "arlo_shift,arlo_shift_reg")]
)
(define_insn "*shiftsi3_compare0"
[(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (match_operator:SI 3 "shift_operator"
- [(match_operand:SI 1 "s_register_operand" "r")
- (match_operand:SI 2 "arm_rhs_operand" "rM")])
+ [(match_operand:SI 1 "s_register_operand" "r,r")
+ (match_operand:SI 2 "arm_rhs_operand" "M,r")])
(const_int 0)))
- (set (match_operand:SI 0 "s_register_operand" "=r")
+ (set (match_operand:SI 0 "s_register_operand" "=r,r")
(match_op_dup 3 [(match_dup 1) (match_dup 2)]))]
"TARGET_32BIT"
"* return arm_output_shift(operands, 1);"
[(set_attr "conds" "set")
(set_attr "shift" "1")
- (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
- (const_string "alu_shift")
- (const_string "alu_shift_reg")))]
+ (set_attr "type" "arlo_shift,arlo_shift_reg")]
)
(define_insn "*shiftsi3_compare0_scratch"
[(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (match_operator:SI 3 "shift_operator"
- [(match_operand:SI 1 "s_register_operand" "r")
- (match_operand:SI 2 "arm_rhs_operand" "rM")])
+ [(match_operand:SI 1 "s_register_operand" "r,r")
+ (match_operand:SI 2 "arm_rhs_operand" "M,r")])
(const_int 0)))
- (clobber (match_scratch:SI 0 "=r"))]
+ (clobber (match_scratch:SI 0 "=r,r"))]
"TARGET_32BIT"
"* return arm_output_shift(operands, 1);"
[(set_attr "conds" "set")
- (set_attr "shift" "1")]
+ (set_attr "shift" "1")
+ (set_attr "type" "shift,shift_reg")]
)
(define_insn "*not_shiftsi"
(set_attr "shift" "1")
(set_attr "insn" "mvn")
(set_attr "arch" "32,a")
- (set_attr "type" "alu_shift,alu_shift_reg")])
+ (set_attr "type" "arlo_shift,arlo_shift_reg")])
(define_insn "*not_shiftsi_compare0"
[(set (reg:CC_NOOV CC_REGNUM)
(set_attr "shift" "1")
(set_attr "insn" "mvn")
(set_attr "arch" "32,a")
- (set_attr "type" "alu_shift,alu_shift_reg")])
+ (set_attr "type" "arlo_shift,arlo_shift_reg")])
(define_insn "*not_shiftsi_compare0_scratch"
[(set (reg:CC_NOOV CC_REGNUM)
(set_attr "shift" "1")
(set_attr "insn" "mvn")
(set_attr "arch" "32,a")
- (set_attr "type" "alu_shift,alu_shift_reg")])
+ (set_attr "type" "arlo_shift,arlo_shift_reg")])
;; We don't really have extzv, but defining this using shifts helps
;; to reduce register pressure later on.
[(if_then_else (eq_attr "is_arch6" "yes")
(const_int 2) (const_int 4))
(const_int 4)])
- (set_attr "type" "simple_alu_shift, load_byte")]
+ (set_attr "type" "extend,load_byte")]
)
(define_insn "*arm_zero_extendhisi2"
"@
#
ldr%(h%)\\t%0, %1"
- [(set_attr "type" "alu_shift,load_byte")
+ [(set_attr "type" "arlo_shift,load_byte")
(set_attr "predicable" "yes")]
)
uxth%?\\t%0, %1
ldr%(h%)\\t%0, %1"
[(set_attr "predicable" "yes")
- (set_attr "type" "simple_alu_shift,load_byte")]
+ (set_attr "type" "extend,load_byte")]
)
(define_insn "*arm_zero_extendhisi2addsi"
(match_operand:SI 2 "s_register_operand" "r")))]
"TARGET_INT_SIMD"
"uxtah%?\\t%0, %2, %1"
- [(set_attr "type" "alu_shift")
+ [(set_attr "type" "arlo_shift")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]
)
#
ldrb\\t%0, %1"
[(set_attr "length" "4,2")
- (set_attr "type" "alu_shift,load_byte")
+ (set_attr "type" "arlo_shift,load_byte")
(set_attr "pool_range" "*,32")]
)
uxtb\\t%0, %1
ldrb\\t%0, %1"
[(set_attr "length" "2")
- (set_attr "type" "simple_alu_shift,load_byte")]
+ (set_attr "type" "extend,load_byte")]
)
(define_insn "*arm_zero_extendqisi2"
#
ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
[(set_attr "length" "8,4")
- (set_attr "type" "alu_shift,load_byte")
+ (set_attr "type" "arlo_shift,load_byte")
(set_attr "predicable" "yes")]
)
"@
uxtb%(%)\\t%0, %1
ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
- [(set_attr "type" "simple_alu_shift,load_byte")
+ [(set_attr "type" "extend,load_byte")
(set_attr "predicable" "yes")]
)
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "insn" "xtab")
- (set_attr "type" "alu_shift")]
+ (set_attr "type" "arlo_shift")]
)
(define_split
[(if_then_else (eq_attr "is_arch6" "yes")
(const_int 2) (const_int 4))
(const_int 4)])
- (set_attr "type" "simple_alu_shift,load_byte")
+ (set_attr "type" "extend,load_byte")
(set_attr "pool_range" "*,1018")]
)
#
ldr%(sh%)\\t%0, %1"
[(set_attr "length" "8,4")
- (set_attr "type" "alu_shift,load_byte")
+ (set_attr "type" "arlo_shift,load_byte")
(set_attr "predicable" "yes")
(set_attr "pool_range" "*,256")
(set_attr "neg_pool_range" "*,244")]
"@
sxth%?\\t%0, %1
ldr%(sh%)\\t%0, %1"
- [(set_attr "type" "simple_alu_shift,load_byte")
+ [(set_attr "type" "extend,load_byte")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "pool_range" "*,256")
#
ldr%(sb%)\\t%0, %1"
[(set_attr "length" "8,4")
- (set_attr "type" "alu_shift,load_byte")
+ (set_attr "type" "arlo_shift,load_byte")
(set_attr "predicable" "yes")
(set_attr "pool_range" "*,256")
(set_attr "neg_pool_range" "*,244")]
"@
sxtb%?\\t%0, %1
ldr%(sb%)\\t%0, %1"
- [(set_attr "type" "simple_alu_shift,load_byte")
+ [(set_attr "type" "extend,load_byte")
(set_attr "predicable" "yes")
(set_attr "pool_range" "*,256")
(set_attr "neg_pool_range" "*,244")]
(match_operand:SI 2 "s_register_operand" "r")))]
"TARGET_INT_SIMD"
"sxtab%?\\t%0, %2, %1"
- [(set_attr "type" "alu_shift")
+ [(set_attr "type" "arlo_shift")
(set_attr "insn" "xtab")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]
(const_int 2)
(if_then_else (eq_attr "is_arch6" "yes")
(const_int 4) (const_int 6))])
- (set_attr "type" "simple_alu_shift,load_byte,load_byte")]
+ (set_attr "type" "extend,load_byte,load_byte")]
)
(define_expand "extendsfdf2"
movw%?\\t%0, %1
ldr%?\\t%0, %1
str%?\\t%1, %0"
- [(set_attr "type" "*,simple_alu_imm,simple_alu_imm,simple_alu_imm,load1,store1")
+ [(set_attr "type" "*,arlo_imm,arlo_imm,arlo_imm,load1,store1")
(set_attr "insn" "mov,mov,mvn,mov,*,*")
(set_attr "predicable" "yes")
(set_attr "pool_range" "*,*,*,*,4096,*")
cmp%?\\t%0, #0
sub%.\\t%0, %1, #0"
[(set_attr "conds" "set")
- (set_attr "type" "simple_alu_imm,simple_alu_imm")]
+ (set_attr "type" "arlo_imm,arlo_imm")]
)
;; Subroutine to store a half word from a register into memory.
(set_attr "neg_pool_range" "*,*,*,244")
(set_attr_alternative "type"
[(if_then_else (match_operand 1 "const_int_operand" "")
- (const_string "simple_alu_imm" )
+ (const_string "arlo_imm" )
(const_string "*"))
- (const_string "simple_alu_imm")
+ (const_string "arlo_imm")
(const_string "store1")
(const_string "load1")])]
)
mvn%?\\t%0, #%B1\\t%@ movhi"
[(set_attr "predicable" "yes")
(set_attr "insn" "mov, mov,mvn")
- (set_attr "type" "simple_alu_imm,*,simple_alu_imm")]
+ (set_attr "type" "arlo_imm,*,arlo_imm")]
)
(define_expand "thumb_movhi_clobber"
str%(b%)\\t%1, %0
ldr%(b%)\\t%0, %1
str%(b%)\\t%1, %0"
- [(set_attr "type" "*,*,simple_alu_imm,simple_alu_imm,simple_alu_imm,load1, store1, load1, store1")
+ [(set_attr "type" "*,*,arlo_imm,arlo_imm,arlo_imm,load1, store1, load1, store1")
(set_attr "insn" "mov,mov,mov,mov,mvn,*,*,*,*")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "yes,yes,yes,no,no,no,no,no,no")
mov\\t%0, %1
mov\\t%0, %1"
[(set_attr "length" "2")
- (set_attr "type" "simple_alu_imm,load1,store1,*,*,simple_alu_imm")
+ (set_attr "type" "arlo_imm,load1,store1,*,*,arlo_imm")
(set_attr "insn" "*,*,*,mov,mov,mov")
(set_attr "pool_range" "*,32,*,*,*,*")
(set_attr "conds" "clob,nocond,nocond,nocond,nocond,clob")])
(set_attr "arch" "t2,t2,any,any")
(set_attr "length" "2,2,4,4")
(set_attr "predicable" "yes")
- (set_attr "type" "*,*,*,simple_alu_imm")]
+ (set_attr "type" "*,*,*,arlo_imm")]
)
(define_insn "*cmpsi_shiftsi"
[(set_attr "conds" "set")
(set_attr "shift" "1")
(set_attr "arch" "32,a")
- (set_attr "type" "alu_shift,alu_shift_reg")])
+ (set_attr "type" "arlo_shift,arlo_shift_reg")])
(define_insn "*cmpsi_shiftsi_swp"
[(set (reg:CC_SWP CC_REGNUM)
[(set_attr "conds" "set")
(set_attr "shift" "1")
(set_attr "arch" "32,a")
- (set_attr "type" "alu_shift,alu_shift_reg")])
+ (set_attr "type" "arlo_shift,arlo_shift_reg")])
(define_insn "*arm_cmpsi_negshiftsi_si"
[(set (reg:CC_Z CC_REGNUM)
"cmn%?\\t%0, %2%S1"
[(set_attr "conds" "set")
(set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
- (const_string "alu_shift")
- (const_string "alu_shift_reg")))
+ (const_string "arlo_shift")
+ (const_string "arlo_shift_reg")))
(set_attr "predicable" "yes")]
)
(set_attr "insn" "mov,mvn,mov,mvn,mov,mov,mvn,mvn")
(set_attr_alternative "type"
[(if_then_else (match_operand 2 "const_int_operand" "")
- (const_string "simple_alu_imm")
+ (const_string "arlo_imm")
(const_string "*"))
- (const_string "simple_alu_imm")
+ (const_string "arlo_imm")
(if_then_else (match_operand 1 "const_int_operand" "")
- (const_string "simple_alu_imm")
+ (const_string "arlo_imm")
(const_string "*"))
- (const_string "simple_alu_imm")
+ (const_string "arlo_imm")
(const_string "*")
(const_string "*")
(const_string "*")
(if_then_else
(match_operand:SI 3 "mult_operator" "")
(const_string "no") (const_string "yes"))])
- (set_attr "type" "alu_shift,alu_shift,alu_shift,alu_shift_reg")])
+ (set_attr "type" "arlo_shift,arlo_shift,arlo_shift,arlo_shift_reg")])
(define_split
[(set (match_operand:SI 0 "s_register_operand" "")
[(set_attr "conds" "set")
(set_attr "shift" "4")
(set_attr "arch" "32,a")
- (set_attr "type" "alu_shift,alu_shift_reg")])
+ (set_attr "type" "arlo_shift,arlo_shift_reg")])
(define_insn "*arith_shiftsi_compare0_scratch"
[(set (reg:CC_NOOV CC_REGNUM)
[(set_attr "conds" "set")
(set_attr "shift" "4")
(set_attr "arch" "32,a")
- (set_attr "type" "alu_shift,alu_shift_reg")])
+ (set_attr "type" "arlo_shift,arlo_shift_reg")])
(define_insn "*sub_shiftsi"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
[(set_attr "predicable" "yes")
(set_attr "shift" "3")
(set_attr "arch" "32,a")
- (set_attr "type" "alu_shift,alu_shift_reg")])
+ (set_attr "type" "arlo_shift,arlo_shift_reg")])
(define_insn "*sub_shiftsi_compare0"
[(set (reg:CC_NOOV CC_REGNUM)
[(set_attr "conds" "set")
(set_attr "shift" "3")
(set_attr "arch" "32,a")
- (set_attr "type" "alu_shift,alu_shift_reg")])
+ (set_attr "type" "arlo_shift,arlo_shift_reg")])
(define_insn "*sub_shiftsi_compare0_scratch"
[(set (reg:CC_NOOV CC_REGNUM)
[(set_attr "conds" "set")
(set_attr "shift" "3")
(set_attr "arch" "32,a")
- (set_attr "type" "alu_shift,alu_shift_reg")])
+ (set_attr "type" "arlo_shift,arlo_shift_reg")])
\f
(define_insn_and_split "*and_scc"
(set_attr "length" "4,4,8,8")
(set_attr_alternative "type"
[(if_then_else (match_operand 3 "const_int_operand" "")
- (const_string "simple_alu_imm" )
+ (const_string "arlo_imm" )
(const_string "*"))
- (const_string "simple_alu_imm")
+ (const_string "arlo_imm")
(const_string "*")
(const_string "*")])]
)
(set_attr "length" "4,4,8,8")
(set_attr_alternative "type"
[(if_then_else (match_operand 3 "const_int_operand" "")
- (const_string "simple_alu_imm" )
+ (const_string "arlo_imm" )
(const_string "*"))
- (const_string "simple_alu_imm")
+ (const_string "arlo_imm")
(const_string "*")
(const_string "*")])]
)
(set_attr "length" "4,8,8")
(set_attr "insn" "mov")
(set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
- (const_string "alu_shift")
- (const_string "alu_shift_reg")))]
+ (const_string "arlo_shift")
+ (const_string "arlo_shift_reg")))]
)
(define_insn "*ifcompare_move_shift"
(set_attr "length" "4,8,8")
(set_attr "insn" "mov")
(set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
- (const_string "alu_shift")
- (const_string "alu_shift_reg")))]
+ (const_string "arlo_shift")
+ (const_string "arlo_shift_reg")))]
)
(define_insn "*ifcompare_shift_shift"
(set (attr "type") (if_then_else
(and (match_operand 2 "const_int_operand" "")
(match_operand 4 "const_int_operand" ""))
- (const_string "alu_shift")
- (const_string "alu_shift_reg")))]
+ (const_string "arlo_shift")
+ (const_string "arlo_shift_reg")))]
)
(define_insn "*ifcompare_not_arith"
;; ALU operations with no shifted operand
(define_insn_reservation "1020alu_op" 1
(and (eq_attr "tune" "arm1020e,arm1022e")
- (eq_attr "type" "alu_reg,simple_alu_imm"))
+ (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
"1020a_e,1020a_m,1020a_w")
;; ALU operations with a shift-by-constant operand
(define_insn_reservation "1020alu_shift_op" 1
(and (eq_attr "tune" "arm1020e,arm1022e")
- (eq_attr "type" "simple_alu_shift,alu_shift"))
+ (eq_attr "type" "extend,arlo_shift"))
"1020a_e,1020a_m,1020a_w")
;; ALU operations with a shift-by-register operand
;; the execute stage.
(define_insn_reservation "1020alu_shift_reg_op" 2
(and (eq_attr "tune" "arm1020e,arm1022e")
- (eq_attr "type" "alu_shift_reg"))
+ (eq_attr "type" "arlo_shift_reg"))
"1020a_e*2,1020a_m,1020a_w")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; ALU operations with no shifted operand
(define_insn_reservation "alu_op" 1
(and (eq_attr "tune" "arm1026ejs")
- (eq_attr "type" "alu_reg,simple_alu_imm"))
+ (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
"a_e,a_m,a_w")
;; ALU operations with a shift-by-constant operand
(define_insn_reservation "alu_shift_op" 1
(and (eq_attr "tune" "arm1026ejs")
- (eq_attr "type" "simple_alu_shift,alu_shift"))
+ (eq_attr "type" "extend,arlo_shift"))
"a_e,a_m,a_w")
;; ALU operations with a shift-by-register operand
;; the execute stage.
(define_insn_reservation "alu_shift_reg_op" 2
(and (eq_attr "tune" "arm1026ejs")
- (eq_attr "type" "alu_shift_reg"))
+ (eq_attr "type" "arlo_shift_reg"))
"a_e*2,a_m,a_w")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; ALU operations with no shifted operand
(define_insn_reservation "11_alu_op" 2
(and (eq_attr "tune" "arm1136js,arm1136jfs")
- (eq_attr "type" "alu_reg,simple_alu_imm"))
+ (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
"e_1,e_2,e_3,e_wb")
;; ALU operations with a shift-by-constant operand
(define_insn_reservation "11_alu_shift_op" 2
(and (eq_attr "tune" "arm1136js,arm1136jfs")
- (eq_attr "type" "simple_alu_shift,alu_shift"))
+ (eq_attr "type" "extend,arlo_shift"))
"e_1,e_2,e_3,e_wb")
;; ALU operations with a shift-by-register operand
;; the shift stage.
(define_insn_reservation "11_alu_shift_reg_op" 3
(and (eq_attr "tune" "arm1136js,arm1136jfs")
- (eq_attr "type" "alu_shift_reg"))
+ (eq_attr "type" "arlo_shift_reg"))
"e_1*2,e_2,e_3,e_wb")
;; alu_ops can start sooner, if there is no shifter dependency
;; ALU operations with no shifted operand
(define_insn_reservation "9_alu_op" 1
(and (eq_attr "tune" "arm926ejs")
- (eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,alu_shift"))
+ (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,extend,arlo_shift"))
"e,m,w")
;; ALU operations with a shift-by-register operand
;; the execute stage.
(define_insn_reservation "9_alu_shift_reg_op" 2
(and (eq_attr "tune" "arm926ejs")
- (eq_attr "type" "alu_shift_reg"))
+ (eq_attr "type" "arlo_shift_reg"))
"e*2,m,w")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Simple ALU without shift
(define_insn_reservation "cortex_a15_alu" 2
(and (eq_attr "tune" "cortexa15")
- (and (eq_attr "type" "alu_reg,simple_alu_imm")
+ (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
(eq_attr "neon_type" "none")))
"ca15_issue1,(ca15_sx1,ca15_sx1_alu)|(ca15_sx2,ca15_sx2_alu)")
;; ALU ops with immediate shift
(define_insn_reservation "cortex_a15_alu_shift" 3
(and (eq_attr "tune" "cortexa15")
- (and (eq_attr "type" "simple_alu_shift,alu_shift")
+ (and (eq_attr "type" "extend,arlo_shift")
(eq_attr "neon_type" "none")))
"ca15_issue1,(ca15_sx1,ca15_sx1+ca15_sx1_shf,ca15_sx1_alu)\
|(ca15_sx2,ca15_sx2+ca15_sx2_shf,ca15_sx2_alu)")
;; ALU ops with register controlled shift
(define_insn_reservation "cortex_a15_alu_shift_reg" 3
(and (eq_attr "tune" "cortexa15")
- (and (eq_attr "type" "alu_shift_reg")
+ (and (eq_attr "type" "arlo_shift_reg")
(eq_attr "neon_type" "none")))
"(ca15_issue2,ca15_sx1+ca15_sx2,ca15_sx1_shf,ca15_sx2_alu)\
|(ca15_issue1,(ca15_issue1+ca15_sx2,ca15_sx1+ca15_sx2_shf)\
(define_insn_reservation "cortex_a5_alu" 2
(and (eq_attr "tune" "cortexa5")
- (eq_attr "type" "alu_reg,simple_alu_imm"))
+ (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
"cortex_a5_ex1")
(define_insn_reservation "cortex_a5_alu_shift" 2
(and (eq_attr "tune" "cortexa5")
- (eq_attr "type" "simple_alu_shift,alu_shift,alu_shift_reg"))
+ (eq_attr "type" "extend,arlo_shift,arlo_shift_reg"))
"cortex_a5_ex1")
;; Forwarding path for unshifted operands.
(define_insn_reservation "cortex_a53_alu" 2
(and (eq_attr "tune" "cortexa53")
- (eq_attr "type" "alu_reg,simple_alu_imm"))
+ (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
"cortex_a53_slot_any")
(define_insn_reservation "cortex_a53_alu_shift" 2
(and (eq_attr "tune" "cortexa53")
- (eq_attr "type" "alu_shift,alu_shift_reg"))
+ (eq_attr "type" "arlo_shift,arlo_shift_reg"))
"cortex_a53_slot_any")
;; Forwarding path for unshifted operands.
;; ALU instruction with an immediate operand can dual-issue.
(define_insn_reservation "cortex_a7_alu_imm" 2
(and (eq_attr "tune" "cortexa7")
- (and (ior (eq_attr "type" "simple_alu_imm")
- (ior (eq_attr "type" "simple_alu_shift")
+ (and (ior (eq_attr "type" "arlo_imm")
+ (ior (eq_attr "type" "extend")
(and (eq_attr "insn" "mov")
(not (eq_attr "length" "8")))))
(eq_attr "neon_type" "none")))
;; with a younger immediate-based instruction.
(define_insn_reservation "cortex_a7_alu_reg" 2
(and (eq_attr "tune" "cortexa7")
- (and (eq_attr "type" "alu_reg")
+ (and (eq_attr "type" "arlo_reg,shift,shift_reg")
(eq_attr "neon_type" "none")))
"cortex_a7_ex1")
(define_insn_reservation "cortex_a7_alu_shift" 2
(and (eq_attr "tune" "cortexa7")
- (and (eq_attr "type" "alu_shift,alu_shift_reg")
+ (and (eq_attr "type" "arlo_shift,arlo_shift_reg")
(eq_attr "neon_type" "none")))
"cortex_a7_ex1")
;; (source read in E2 and destination available at the end of that cycle).
(define_insn_reservation "cortex_a8_alu" 2
(and (eq_attr "tune" "cortexa8")
- (ior (and (and (eq_attr "type" "alu_reg,simple_alu_imm")
+ (ior (and (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
(eq_attr "neon_type" "none"))
(not (eq_attr "insn" "mov,mvn")))
(eq_attr "insn" "clz")))
(define_insn_reservation "cortex_a8_alu_shift" 2
(and (eq_attr "tune" "cortexa8")
- (and (eq_attr "type" "simple_alu_shift,alu_shift")
+ (and (eq_attr "type" "extend,arlo_shift")
(not (eq_attr "insn" "mov,mvn"))))
"cortex_a8_default")
(define_insn_reservation "cortex_a8_alu_shift_reg" 2
(and (eq_attr "tune" "cortexa8")
- (and (eq_attr "type" "alu_shift_reg")
+ (and (eq_attr "type" "arlo_shift_reg")
(not (eq_attr "insn" "mov,mvn"))))
"cortex_a8_default")
(define_insn_reservation "cortex_a8_mov" 1
(and (eq_attr "tune" "cortexa8")
- (and (eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,alu_shift,alu_shift_reg")
+ (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,extend,arlo_shift,arlo_shift_reg")
(eq_attr "insn" "mov,mvn")))
"cortex_a8_default")
;; which can go down E2 without any problem.
(define_insn_reservation "cortex_a9_dp" 2
(and (eq_attr "tune" "cortexa9")
- (ior (and (eq_attr "type" "alu_reg,simple_alu_imm")
+ (ior (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
(eq_attr "neon_type" "none"))
- (and (and (eq_attr "type" "alu_shift_reg, simple_alu_shift,alu_shift")
+ (and (and (eq_attr "type" "arlo_shift_reg,extend,arlo_shift")
(eq_attr "insn" "mov"))
(eq_attr "neon_type" "none"))))
"cortex_a9_p0_default|cortex_a9_p1_default")
;; An instruction using the shifter will go down E1.
(define_insn_reservation "cortex_a9_dp_shift" 3
(and (eq_attr "tune" "cortexa9")
- (and (eq_attr "type" "alu_shift_reg, simple_alu_shift,alu_shift")
+ (and (eq_attr "type" "arlo_shift_reg,extend,arlo_shift")
(not (eq_attr "insn" "mov"))))
"cortex_a9_p0_shift | cortex_a9_p1_shift")
;; ALU and multiply is one cycle.
(define_insn_reservation "cortex_m4_alu" 1
(and (eq_attr "tune" "cortexm4")
- (ior (eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,\
- alu_shift,alu_shift_reg")
+ (ior (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,extend,\
+ arlo_shift,arlo_shift_reg")
(ior (eq_attr "mul32" "yes")
(eq_attr "mul64" "yes"))))
"cortex_m4_ex")
;; for the purposes of the dual-issue constraints above.
(define_insn_reservation "cortex_r4_alu" 2
(and (eq_attr "tune_cortexr4" "yes")
- (and (eq_attr "type" "alu_reg,simple_alu_imm")
+ (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
(not (eq_attr "insn" "mov"))))
"cortex_r4_alu")
(define_insn_reservation "cortex_r4_mov" 2
(and (eq_attr "tune_cortexr4" "yes")
- (and (eq_attr "type" "alu_reg,simple_alu_imm")
+ (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
(eq_attr "insn" "mov")))
"cortex_r4_mov")
(define_insn_reservation "cortex_r4_alu_shift" 2
(and (eq_attr "tune_cortexr4" "yes")
- (eq_attr "type" "simple_alu_shift,alu_shift"))
+ (eq_attr "type" "extend,arlo_shift"))
"cortex_r4_alu")
(define_insn_reservation "cortex_r4_alu_shift_reg" 2
(and (eq_attr "tune_cortexr4" "yes")
- (eq_attr "type" "alu_shift_reg"))
+ (eq_attr "type" "arlo_shift_reg"))
"cortex_r4_alu_shift_reg")
;; An ALU instruction followed by an ALU instruction with no early dep.
;; ALU operations
(define_insn_reservation "526_alu_op" 1
(and (eq_attr "tune" "fa526")
- (eq_attr "type" "alu_reg,simple_alu_imm"))
+ (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
"fa526_core")
(define_insn_reservation "526_alu_shift_op" 2
(and (eq_attr "tune" "fa526")
- (eq_attr "type" "simple_alu_shift,alu_shift,alu_shift_reg"))
+ (eq_attr "type" "extend,arlo_shift,arlo_shift_reg"))
"fa526_core")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; ALU operations
(define_insn_reservation "606te_alu_op" 1
(and (eq_attr "tune" "fa606te")
- (eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,alu_shift,alu_shift_reg"))
+ (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,extend,arlo_shift,arlo_shift_reg"))
"fa606te_core")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; ALU operations
(define_insn_reservation "626te_alu_op" 1
(and (eq_attr "tune" "fa626,fa626te")
- (eq_attr "type" "alu_reg,simple_alu_imm"))
+ (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
"fa626te_core")
(define_insn_reservation "626te_alu_shift_op" 2
(and (eq_attr "tune" "fa626,fa626te")
- (eq_attr "type" "simple_alu_shift,alu_shift,alu_shift_reg"))
+ (eq_attr "type" "extend,arlo_shift,arlo_shift_reg"))
"fa626te_core")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Other ALU instructions 2 cycles.
(define_insn_reservation "726te_alu_op" 1
(and (eq_attr "tune" "fa726te")
- (and (eq_attr "type" "alu_reg,simple_alu_imm")
+ (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
(not (eq_attr "insn" "mov,mvn"))))
"fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
;; it takes 3 cycles.
(define_insn_reservation "726te_alu_shift_op" 3
(and (eq_attr "tune" "fa726te")
- (and (eq_attr "type" "simple_alu_shift,alu_shift")
+ (and (eq_attr "type" "extend,arlo_shift")
(not (eq_attr "insn" "mov,mvn"))))
"fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
(define_insn_reservation "726te_alu_shift_reg_op" 3
(and (eq_attr "tune" "fa726te")
- (and (eq_attr "type" "alu_shift_reg")
+ (and (eq_attr "type" "arlo_shift_reg")
(not (eq_attr "insn" "mov,mvn"))))
"fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; ALU operations
(define_insn_reservation "mp626_alu_op" 1
(and (eq_attr "tune" "fmp626")
- (eq_attr "type" "alu_reg,simple_alu_imm"))
+ (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
"fmp626_core")
(define_insn_reservation "mp626_alu_shift_op" 2
(and (eq_attr "tune" "fmp626")
- (eq_attr "type" "simple_alu_shift,alu_shift,alu_shift_reg"))
+ (eq_attr "type" "extend,arlo_shift,arlo_shift_reg"))
"fmp626_core")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_insn_reservation "pj4_alu_e1" 1
(and (eq_attr "tune" "marvell_pj4")
- (eq_attr "type" "simple_alu_imm,alu_reg")
+ (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
(not (eq_attr "conds" "set"))
(eq_attr "insn" "mov,mvn"))
"pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_alu_e1_conds" 4
(and (eq_attr "tune" "marvell_pj4")
- (eq_attr "type" "simple_alu_imm,alu_reg")
+ (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
(eq_attr "conds" "set")
(eq_attr "insn" "mov,mvn"))
"pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_alu" 1
(and (eq_attr "tune" "marvell_pj4")
- (eq_attr "type" "simple_alu_imm,alu_reg")
+ (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
(not (eq_attr "conds" "set"))
(not (eq_attr "insn" "mov,mvn")))
"pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_alu_conds" 4
(and (eq_attr "tune" "marvell_pj4")
- (eq_attr "type" "simple_alu_imm,alu_reg")
+ (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
(eq_attr "conds" "set")
(not (eq_attr "insn" "mov,mvn")))
"pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_shift" 1
(and (eq_attr "tune" "marvell_pj4")
- (eq_attr "type" "alu_shift,alu_shift_reg,simple_alu_shift")
+ (eq_attr "type" "arlo_shift,arlo_shift_reg,extend")
(not (eq_attr "conds" "set"))
(eq_attr "shift" "1")) "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_shift_conds" 4
(and (eq_attr "tune" "marvell_pj4")
- (eq_attr "type" "alu_shift,alu_shift_reg,simple_alu_shift")
+ (eq_attr "type" "arlo_shift,arlo_shift_reg,extend")
(eq_attr "conds" "set")
(eq_attr "shift" "1")) "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_alu_shift" 1
(and (eq_attr "tune" "marvell_pj4")
(not (eq_attr "conds" "set"))
- (eq_attr "type" "alu_shift,alu_shift_reg,simple_alu_shift"))
+ (eq_attr "type" "arlo_shift,arlo_shift_reg,extend"))
"pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_alu_shift_conds" 4
(and (eq_attr "tune" "marvell_pj4")
(eq_attr "conds" "set")
- (eq_attr "type" "alu_shift,alu_shift_reg,simple_alu_shift"))
+ (eq_attr "type" "arlo_shift,arlo_shift_reg,extend"))
"pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)")
(define_bypass 2 "pj4_alu_shift,pj4_shift"
}
}
[(set_attr "neon_type" "neon_int_1,*,neon_vmov,*,neon_mrrc,neon_mcr_2_mcrr,*,*,*")
- (set_attr "type" "*,f_stored,*,f_loadd,*,*,alu_reg,load2,store2")
+ (set_attr "type" "*,f_stored,*,f_loadd,*,*,arlo_reg,load2,store2")
(set_attr "insn" "*,*,*,*,*,*,mov,*,*")
(set_attr "length" "4,4,4,4,4,4,8,8,8")
(set_attr "arm_pool_range" "*,*,*,1020,*,*,*,1020,*")
}
[(set_attr "neon_type" "neon_int_1,neon_stm_2,neon_vmov,neon_ldm_2,\
neon_mrrc,neon_mcr_2_mcrr,*,*,*")
- (set_attr "type" "*,*,*,*,*,*,alu_reg,load4,store4")
+ (set_attr "type" "*,*,*,*,*,*,arlo_reg,load4,store4")
(set_attr "insn" "*,*,*,*,*,*,mov,*,*")
(set_attr "length" "4,8,4,8,8,8,16,8,16")
(set_attr "arm_pool_range" "*,*,*,1020,*,*,*,1020,*")
"bic%?\\t%0, %1, %2%S4"
[(set_attr "predicable" "yes")
(set_attr "shift" "2")
- (set_attr "type" "alu_shift")]
+ (set_attr "type" "arlo_shift")]
)
(define_insn_and_split "*thumb2_smaxsi3"
ldr%?\\t%0, %1
str%?\\t%1, %0
str%?\\t%1, %0"
- [(set_attr "type" "*,simple_alu_imm,simple_alu_imm,simple_alu_imm,*,load1,load1,store1,store1")
+ [(set_attr "type" "*,arlo_imm,arlo_imm,arlo_imm,*,load1,load1,store1,store1")
(set_attr "length" "2,4,2,4,4,4,4,4,4")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no")
"cmn%?\\t%0, %1%S3"
[(set_attr "conds" "set")
(set_attr "shift" "1")
- (set_attr "type" "alu_shift")]
+ (set_attr "type" "arlo_shift")]
)
(define_insn_and_split "*thumb2_mov_scc"
"@
sxtb%?\\t%0, %1
ldr%(sb%)\\t%0, %1"
- [(set_attr "type" "simple_alu_shift,load_byte")
+ [(set_attr "type" "extend,load_byte")
(set_attr "predicable" "yes")
(set_attr "pool_range" "*,4094")
(set_attr "neg_pool_range" "*,250")]
"@
uxth%?\\t%0, %1
ldr%(h%)\\t%0, %1"
- [(set_attr "type" "simple_alu_shift,load_byte")
+ [(set_attr "type" "extend,load_byte")
(set_attr "predicable" "yes")
(set_attr "pool_range" "*,4094")
(set_attr "neg_pool_range" "*,250")]
"@
uxtb%(%)\\t%0, %1
ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
- [(set_attr "type" "simple_alu_shift,load_byte")
+ [(set_attr "type" "extend,load_byte")
(set_attr "predicable" "yes")
(set_attr "pool_range" "*,4094")
(set_attr "neg_pool_range" "*,250")]
(set_attr "shift" "1")
(set_attr "length" "2")
(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
- (const_string "alu_shift")
- (const_string "alu_shift_reg")))]
+ (const_string "arlo_shift")
+ (const_string "arlo_shift_reg")))]
)
(define_insn "*thumb2_mov<mode>_shortim"
"
[(set_attr "conds" "set")
(set_attr "length" "2,2,4,4")
- (set_attr "type" "simple_alu_imm,*,simple_alu_imm,*")]
+ (set_attr "type" "arlo_imm,*,arlo_imm,*")]
)
(define_insn "*thumb2_mulsi_short"
"orn%?\\t%0, %1, %2%S4"
[(set_attr "predicable" "yes")
(set_attr "shift" "2")
- (set_attr "type" "alu_shift")]
+ (set_attr "type" "arlo_shift")]
)
(define_peephole2
}
"
[(set_attr "predicable" "yes")
- (set_attr "type" "*,*,simple_alu_imm,simple_alu_imm,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
+ (set_attr "type" "*,*,arlo_imm,arlo_imm,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
(set_attr "neon_type" "*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*")
(set_attr "insn" "mov,mov,mvn,mov,*,*,*,*,*,*,*")
(set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*")
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