sv: fix support wire and var data type modifiers

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 0f7f2a57adb8000c705ec6b73411331662bc91c5..2886db0e56a134963cfc2fa06d82c2a1f5b5cb03 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -664,28 +664,33 @@ wire_type_token:
                astbuf3->children.push_back(new AstNode(AST_WIRETYPE));
                astbuf3->children.back()->str = *$1;
        } |
-       TOK_WIRE {
-       } |
        TOK_WOR {
                astbuf3->is_wor = true;
        } |
        TOK_WAND {
                astbuf3->is_wand = true;
        } |
+       // wires
+       TOK_WIRE {
+       } |
+       TOK_WIRE logic_type {
+       } |
+       // regs
        TOK_REG {
                astbuf3->is_reg = true;
        } |
-       TOK_LOGIC {
-               astbuf3->is_logic = true;
+       TOK_VAR TOK_REG {
+               astbuf3->is_reg = true;
        } |
+       // logics
        TOK_VAR {
                astbuf3->is_logic = true;
        } |
-       TOK_INTEGER {
-               astbuf3->is_reg = true;
-               astbuf3->range_left = 31;
-               astbuf3->range_right = 0;
-               astbuf3->is_signed = true;
+       TOK_VAR logic_type {
+               astbuf3->is_logic = true;
+       } |
+       logic_type {
+               astbuf3->is_logic = true;
        } |
        TOK_GENVAR {
                astbuf3->type = AST_GENVAR;
@@ -695,6 +700,15 @@ wire_type_token:
                astbuf3->range_right = 0;
        };
 
+logic_type:
+       TOK_LOGIC {
+       } |
+       TOK_INTEGER {
+               astbuf3->range_left = 31;
+               astbuf3->range_right = 0;
+               astbuf3->is_signed = true;
+       };
+
 non_opt_range:
        '[' expr ':' expr ']' {
                $$ = new AstNode(AST_RANGE);

diff --git a/tests/verilog/wire_and_var.sv b/tests/verilog/wire_and_var.sv
new file mode 100644 (file)
index 0000000..79c7c04
--- /dev/null
+++ b/tests/verilog/wire_and_var.sv
@@ -0,0 +1,33 @@
+`define TEST(kwd) \
+       kwd kwd``_1; \
+       kwd kwd``_2; \
+       initial kwd``_1 = 1; \
+       assign kwd``_2 = 1;
+
+`define TEST_VAR(kwd) \
+       var kwd var_``kwd``_1; \
+       var kwd var_``kwd``_2; \
+       initial var_``kwd``_1 = 1; \
+       assign var_``kwd``_2 = 1;
+
+`define TEST_WIRE(kwd) \
+       wire kwd wire_``kwd``_1; \
+       wire kwd wire_``kwd``_2; \
+       initial wire_``kwd``_1 = 1; \
+       assign wire_``kwd``_2 = 1;
+
+module top;
+
+`TEST(wire) // wire assigned in a block
+`TEST(reg) // reg assigned in a continuous assignment
+`TEST(logic)
+`TEST(integer)
+
+`TEST_VAR(reg) // reg assigned in a continuous assignment
+`TEST_VAR(logic)
+`TEST_VAR(integer)
+
+`TEST_WIRE(logic) // wire assigned in a block
+`TEST_WIRE(integer) // wire assigned in a block
+
+endmodule

diff --git a/tests/verilog/wire_and_var.ys b/tests/verilog/wire_and_var.ys
new file mode 100644 (file)
index 0000000..9359a9d
--- /dev/null
+++ b/tests/verilog/wire_and_var.ys
@@ -0,0 +1,9 @@
+logger -expect warning "wire '\\wire_1' is assigned in a block" 1
+logger -expect warning "reg '\\reg_2' is assigned in a continuous assignment" 1
+
+logger -expect warning "reg '\\var_reg_2' is assigned in a continuous assignment" 1
+
+logger -expect warning "wire '\\wire_logic_1' is assigned in a block" 1
+logger -expect warning "wire '\\wire_integer_1' is assigned in a block" 1
+
+read_verilog -sv wire_and_var.sv