dev-arm, fastmodel: Rewrite Gic.interruptCells
authorGiacomo Travaglini <giacomo.travaglini@arm.com>
Fri, 16 Oct 2020 10:09:44 +0000 (11:09 +0100)
committerGiacomo Travaglini <giacomo.travaglini@arm.com>
Sat, 17 Oct 2020 10:21:08 +0000 (10:21 +0000)
The affinity number (aka PPI partition) is used differently
in GICv2 and GICv3. In GICv2 it is ORed to the triggering type
(3rd cell), whereas it is encoded in the 4th cell in GICv3

Change-Id: I36e45d4ec5fb39befa1a271b531dfed2d8e56c10
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36235
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/arch/arm/fastmodel/GIC/FastModelGIC.py
src/dev/arm/Gic.py

index ddcf728f8cdd7f45d2afc2a1521734416b346de7..3298be944408ea47a4959d89c38afd1bd78f3764 100644 (file)
@@ -514,7 +514,7 @@ class FastModelGIC(BaseGic):
 
         return ranges
 
-    def interruptCells(self, int_type, int_num, int_flag):
+    def interruptCells(self, int_type, int_num, int_trigger, int_affinity=0):
         """
         Interupt cells generation helper:
         Following specifications described in
@@ -525,7 +525,7 @@ class FastModelGIC(BaseGic):
         assert len(prop) >= 3
         prop[0] = int_type
         prop[1] = int_num
-        prop[2] = int_flag
+        prop[2] = int_trigger
         return prop
 
     def generateDeviceTree(self, state):
@@ -552,7 +552,7 @@ class FastModelGIC(BaseGic):
         node.append(FdtPropertyWords("reg", regs))
         # Maintenance interrupt (PPI 25).
         node.append(FdtPropertyWords("interrupts",
-            self.interruptCells(1, 9, 0xf04)))
+            self.interruptCells(1, 9, 0x4)))
 
         node.appendPhandle(self)
 
index 17a553fcc3bc496cb45867e485f3072499bfafdc..987a6e0abff377b59bda510c045fee6cb32dce7f 100644 (file)
@@ -60,7 +60,7 @@ class BaseGic(PioDevice):
     gicv_iidr = Param.UInt32(0,
         "VM CPU Interface Identification Register")
 
-    def interruptCells(self, int_type, int_num, int_flag):
+    def interruptCells(self, int_type, int_num, int_trigger, partition=None):
         """
         Interupt cells generation helper:
         Following specifications described in
@@ -68,7 +68,16 @@ class BaseGic(PioDevice):
         Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
         """
         assert self._state.interrupt_cells == 3
-        return [ int_type, int_num, int_flag ]
+
+        # Check for affinity in case of PPI. If there is no PPI
+        # partitioning, set the affinity to target all CPUs
+        # (affinity = 0xf00)
+        if partition is None and int_type == ArmPPI._LINUX_ID:
+            affinity = 0xf00
+        else:
+            affinity = 0
+
+        return [ int_type, int_num, affinity | int_trigger ]
 
 class ArmInterruptType(ScopedEnum):
     """
@@ -99,11 +108,15 @@ class ArmSPI(ArmInterruptPin):
     cxx_header = "dev/arm/base_gic.hh"
     cxx_class = "ArmSPIGen"
 
+    _LINUX_ID = 0
+
 class ArmPPI(ArmInterruptPin):
     type = 'ArmPPI'
     cxx_header = "dev/arm/base_gic.hh"
     cxx_class = "ArmPPIGen"
 
+    _LINUX_ID = 1
+
 class GicV2(BaseGic):
     type = 'GicV2'
     cxx_header = "dev/arm/gic_v2.hh"
@@ -237,7 +250,7 @@ class Gicv3(BaseGic):
 
     gicv4 = Param.Bool(True, "GICv4 extension available")
 
-    def interruptCells(self, int_type, int_num, int_flag):
+    def interruptCells(self, int_type, int_num, int_trigger, partition=None):
         """
         Interupt cells generation helper:
         Following specifications described in
@@ -248,7 +261,7 @@ class Gicv3(BaseGic):
         assert len(prop) >= 3
         prop[0] = int_type
         prop[1] = int_num
-        prop[2] = int_flag
+        prop[2] = int_trigger
         return prop
 
     def generateDeviceTree(self, state):
@@ -272,7 +285,7 @@ class Gicv3(BaseGic):
 
         node.append(FdtPropertyWords("reg", regs))
         node.append(FdtPropertyWords("interrupts",
-            self.interruptCells(1, int(self.maint_int.num)-16, 0xf04)))
+            self.interruptCells(1, int(self.maint_int.num)-16, 0x4)))
 
         node.appendPhandle(self)